专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100260002A1 Circuit and Method for Small Swing Memory Signals 有权
标题翻译：小型摆动存储器信号的电路和方法
公开(公告)号：US20100260002A1
公开(公告)日：2010-10-14
申请号：US12687571
申请日：2010-01-14
申请人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C7/02 , G11C8/00
CPC分类号： G11C8/12 , G11C11/413
摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.
摘要翻译：描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。多个存储单元形成为多个存储体中的阵列。每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。公开了向存储器单元提供小的摆动全局位线信号的方法。在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

2. 发明授权

US08116149B2 Circuit and method for small swing memory signals 有权
标题翻译：小摆动记忆信号的电路和方法
公开(公告)号：US08116149B2
公开(公告)日：2012-02-14
申请号：US12687571
申请日：2010-01-14
申请人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C7/06
CPC分类号： G11C8/12 , G11C11/413
摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.
摘要翻译：描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。多个存储单元形成为多个存储体中的阵列。每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。公开了向存储器单元提供小的摆动全局位线信号的方法。在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

3. 发明授权

US08331132B2 Adaptive write bit line and word line adjusting mechanism for memory 有权
标题翻译：适应性写入位线和字线调整机制用于存储器
公开(公告)号：US08331132B2
公开(公告)日：2012-12-11
申请号：US12849570
申请日：2010-08-03
申请人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C11/24 , G11C7/00 , G11C8/00
CPC分类号： G11C7/00 , G11C7/20 , G11C8/08 , G11C11/413 , G11C2207/2254
摘要： A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.
摘要翻译：存储器包括耦合到写位线或字线的电容器。初始化器被配置为初始化电容器和写位线或字线之间的第一节点处的电压电平。初始电平调节器被配置为调节电容器的一个端子处的第二节点的电压电平。脉冲发生器，被配置为向初始电平调节器提供脉冲以控制初始电平调节器。升压信号被配置为提供给与第一节点相对的电容器的另一个端子上的第三节点，以提高写入位线的低于地的电压电平，或将字线的电压电平提高到高于功率电源电压。

4. 发明申请

US20120188838A1 MEMORY WITH WORD-LINE SEGMENT ACCESS 有权
标题翻译：使用WORD-LINE SEGMENT访问的记忆
公开(公告)号：US20120188838A1
公开(公告)日：2012-07-26
申请号：US13010039
申请日：2011-01-20
申请人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/12 , G11C8/14 , G11C11/418 , G11C11/419
摘要： A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.
摘要翻译：存储器包括一行比特单元，包括第一多个比特单元和第二多个比特单元。第一字线段驱动器连接到第一多个位单元。第二字线段驱动器连接到第二多个位单元。第一和第二字线段驱动器被选择性地可操作用于一次激活第一和第二多个位单元之一以排除其他多个位单元。共享读出放大器耦合到第一多个位单元和第二多个位单元中的至少一个位单元中的至少一个。共享读出放大器被配置为在给定时间从其相应的字线段驱动器接收由一个第一或第二位单元中的哪一个激活的信号。

5. 发明授权

US08631365B2 Memory building blocks and memory design using automatic design tools 有权
标题翻译：使用自动设计工具的内存构建块和内存设计
公开(公告)号：US08631365B2
公开(公告)日：2014-01-14
申请号：US13461571
申请日：2012-05-01
申请人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
发明人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.
摘要翻译：存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由（APR）和时序分析。

6. 发明授权

US08437215B2 Memory with word-line segment access 有权
标题翻译：具有字段段访问的存储器
公开(公告)号：US08437215B2
公开(公告)日：2013-05-07
申请号：US13010039
申请日：2011-01-20
申请人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/12 , G11C8/14 , G11C11/418 , G11C11/419
摘要： A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.
摘要翻译：存储器包括一行比特单元，包括第一多个比特单元和第二多个比特单元。第一字线段驱动器连接到第一多个位单元。第二字线段驱动器连接到第二多个位单元。第一和第二字线段驱动器被选择性地可操作用于一次激活第一和第二多个位单元之一以排除其他多个位单元。共享读出放大器耦合到第一多个位单元和第二多个位单元中的至少一个位单元中的至少一个。共享读出放大器被配置为在给定时间从其相应的字线段驱动器接收由一个第一或第二位单元中的哪一个激活的信号。

7. 发明申请

US20110041109A1 MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS 有权
标题翻译：使用自动设计工具的存储器构建块和存储器设计
公开(公告)号：US20110041109A1
公开(公告)日：2011-02-17
申请号：US12825960
申请日：2010-06-29
申请人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
发明人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.
摘要翻译：存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由（APR）和时序分析。

8. 发明授权

US08185851B2 Memory building blocks and memory design using automatic design tools 有权
标题翻译：使用自动设计工具的内存构建块和内存设计
公开(公告)号：US08185851B2
公开(公告)日：2012-05-22
申请号：US12825960
申请日：2010-06-29
申请人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
发明人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.
摘要翻译：存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由（APR）和时序分析。

9. 发明申请

US20120033517A1 ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY 有权
标题翻译：自适应写入线和字线调整机制
公开(公告)号：US20120033517A1
公开(公告)日：2012-02-09
申请号：US12849570
申请日：2010-08-03
申请人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/20 , G11C8/08 , G11C11/413 , G11C2207/2254
摘要： A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.
摘要翻译：存储器包括耦合到写位线或字线的电容器。初始化器被配置为初始化电容器和写位线或字线之间的第一节点处的电压电平。初始电平调节器被配置为调节电容器的一个端子处的第二节点的电压电平。脉冲发生器，被配置为向初始电平调节器提供脉冲以控制初始电平调节器。升压信号被配置为提供给与第一节点相对的电容器的另一个端子上的第三节点，以提高写入位线的低于地的电压电平，或将字线的电压电平提高到高于功率电源电压。

10. 发明授权

US08560997B1 Conditional cell placement 有权
标题翻译：条件细胞放置
公开(公告)号：US08560997B1
公开(公告)日：2013-10-15
申请号：US13557578
申请日：2012-07-25
申请人： Ping-Lin Yang , Ming-Zhang Kuo , Cheng-Chung Lin , Jimmy Hsiao , Jia-Rong Hsu
发明人： Ping-Lin Yang , Ming-Zhang Kuo , Cheng-Chung Lin , Jimmy Hsiao , Jia-Rong Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.
摘要翻译：其中还提供了一种或多种用于条件单元放置的技术。在一个实施例中，为第一小区创建条件边界。例如，条件边界使得能够基于条件放置规则相对于第二单元放置第一单元。在一个实施例中，基于第一情况，第一小区相对于第二小区以第一方式放置。在第二种情况下，与第一种情况不同，第一单元相对于第二单元以第二种方式放置。以这种方式，提供条件单元布置，从而提供例如关于半导体制造的灵活性和改进的布局效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式