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    • 10. 发明授权
    • Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance
    • 具有良好的界面性能的超薄高K栅极电介质,可提高半导体器件的性能
    • US06911707B2
    • 2005-06-28
    • US09207972
    • 1998-12-09
    • Mark I. GardnerDim-Lee KwongH. Jim Fulford, Jr.
    • Mark I. GardnerDim-Lee KwongH. Jim Fulford, Jr.
    • H01L21/28H01L21/314H01L29/51H01L29/76
    • H01L21/28185H01L21/28194H01L21/28202H01L21/3144H01L29/513H01L29/517H01L29/518
    • An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.
    • 提供具有渐变介电常数的超薄栅极电介质及其形成方法。 认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。 在半导体衬底上形成薄的含氮氧化物,优选具有小于约10埃的厚度。 可以在含氮氧化物上形成厚度小于约30埃的氮化硅层。 氧化物和氮化物层在氨和一氧化二氮环境中退火,并且使用流动气体蚀刻工艺来减少氮化物层的厚度。 与二氧化硅电介质相比,所得到的双层栅极电介质被认为提供增加的电容,同时保持与底层衬底的有利的界面性质。 在替代实施例中,用不同的高介电常数材料代替氮化硅。 或者,可以使用氮化物和不同的高介电常数材料,从而形成三层电介质。