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1. 发明授权

US08546885B2 Metal gate electrode of a field effect transistor 有权
标题翻译：场效应晶体管的金属栅电极
公开(公告)号：US08546885B2
公开(公告)日：2013-10-01
申请号：US13189732
申请日：2011-07-25
申请人： Cheng-Hao Hou , Peng-Soon Lim , Da-Yuan Lee , Xiong-Fei Yu , Chun-Yuan Chou , Fan-Yi Hsu , Jian-Hao Chen , Kuang-Yuan Hsu
发明人： Cheng-Hao Hou , Peng-Soon Lim , Da-Yuan Lee , Xiong-Fei Yu , Chun-Yuan Chou , Fan-Yi Hsu , Jian-Hao Chen , Kuang-Yuan Hsu
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.
摘要翻译：公开了集成电路制造，更具体地说，公开了具有低电阻金属栅电极的场效应晶体管。场效应晶体管的金属栅电极的示例性结构包括由第一金属材料形成的下部，其中下部具有凹部，底部和侧壁部分，其中每个侧壁部分具有第一宽度; 以及由第二金属材料形成的上部，其中所述上部具有突起和主体部分，其中所述主体部分具有第二宽度，其中所述突起延伸到所述凹部中，其中所述第二宽度与所述第一宽度的比率宽度为约5至10。

2. 发明授权

US08580698B2 Method for fabricating a gate dielectric layer 有权
标题翻译：栅极电介质层的制造方法
公开(公告)号：US08580698B2
公开(公告)日：2013-11-12
申请号：US12760297
申请日：2010-04-14
申请人： Wei-Yang Lee , Xiong-Fei Yu , Jian-Hao Chen , Cheng-Hao Hou , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Xiong-Fei Yu , Jian-Hao Chen , Cheng-Hao Hou , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/31
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/0228 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6659
摘要： A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
摘要翻译：一种用于制造栅极电介质层的方法包括在衬底上形成高k电介质层; 通过原子层沉积工艺在高k电介质层上形成含氧层; 对含氧层进行惰性等离子体处理。

3. 发明授权

US08847333B2 Techniques providing metal gate devices with multiple barrier layers 有权
标题翻译：提供具有多个阻挡层的金属栅极器件的技术
公开(公告)号：US08847333B2
公开(公告)日：2014-09-30
申请号：US13224033
申请日：2011-09-01
申请人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuang-Yuan Hsu , Jeff J. Xu
发明人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuang-Yuan Hsu , Jeff J. Xu
IPC分类号： H01L29/76 , H01L29/51 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76846 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。

4. 发明申请

US20110081774A1 METHODS FOR A GATE REPLACEMENT PROCESS 有权
标题翻译：门更换过程的方法
公开(公告)号：US20110081774A1
公开(公告)日：2011-04-07
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/28
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

5. 发明授权

US08952458B2 Gate dielectric layer having interfacial layer and high-K dielectric over the interfacial layer 有权
标题翻译：栅介质层在界面层上具有界面层和高K电介质
公开(公告)号：US08952458B2
公开(公告)日：2015-02-10
申请号：US13086491
申请日：2011-04-14
申请人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/70 , H01L21/02 , H01L21/8238 , H01L29/423 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/66477 , H01L21/28185 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/66545
摘要： A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.
摘要翻译：一种半导体器件包括具有第一有源区，第一有源区上的第一栅结构的衬底，其中第一栅结构包括具有凸顶表面的第一界面层，第一界面层上的第一高k电介质，以及在第一高k电介质上的第一栅电极。

6. 发明授权

US08367563B2 Methods for a gate replacement process 有权
标题翻译：门更换过程的方法
公开(公告)号：US08367563B2
公开(公告)日：2013-02-05
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

7. 发明授权

US08334197B2 Method of fabricating high-k/metal gate device 有权
标题翻译：制造高k /金属栅极器件的方法
公开(公告)号：US08334197B2
公开(公告)日：2012-12-18
申请号：US12639630
申请日：2009-12-16
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
IPC分类号： H01L21/4763
CPC分类号： H01L21/28185 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.
摘要翻译：本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

8. 发明申请

US20110143529A1 METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE 有权
标题翻译：制造高K /金属栅极器件的方法
公开(公告)号：US20110143529A1
公开(公告)日：2011-06-16
申请号：US12639630
申请日：2009-12-16
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
IPC分类号： H01L21/28
CPC分类号： H01L21/28185 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.
摘要翻译：本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

9. 发明申请

US20110256682A1 Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device 审中-公开
标题翻译：用于半导体器件的多沉积，多处理电介质层
公开(公告)号：US20110256682A1
公开(公告)日：2011-10-20
申请号：US12761159
申请日：2010-04-15
申请人： Xiong-Fei Yu , Wei-Yang Lee , Da-Yuan Lee , Kuang-Yuan Hsu , Yuan-Hung Chiu , Hun-Jan Tao , Hongyu Yu , Wu Ling
发明人： Xiong-Fei Yu , Wei-Yang Lee , Da-Yuan Lee , Kuang-Yuan Hsu , Yuan-Hung Chiu , Hun-Jan Tao , Hongyu Yu , Wu Ling
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/823857 , H01L29/513 , H01L29/66545
摘要： A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O2 and/or O3. A second high-k dielectric layer is formed on the treated first high-k dielectric layer. A second treatment is performed on the second high-k dielectric layer. In an embodiment, the high-k dielectric layer forms a gate dielectric layer of a field effect transistor.
摘要翻译：提供了制造半导体器件的方法。提供半导体衬底。在半导体衬底上形成第一高k电介质层。在高k电介质层上进行第一处理。在一个实施方案中，该处理包括在存在O 2和/或O 3的情况下的UV辐射。在被处理的第一高k电介质层上形成第二高k电介质层。对第二高k电介质层进行第二处理。在一个实施例中，高k电介质层形成场效应晶体管的栅介质层。

10. 发明授权

US09048334B2 Metal gate structure 有权
标题翻译：金属门结构
公开(公告)号：US09048334B2
公开(公告)日：2015-06-02
申请号：US13214996
申请日：2011-08-22
申请人： Peng-Soon Lim , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/28 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42376 , H01L21/28114 , H01L21/28247 , H01L21/285 , H01L21/2855 , H01L21/31105 , H01L21/823456 , H01L29/4236 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.
摘要翻译：金属栅极结构包括部分地填充金属栅极结构的沟槽的金属层。金属层包括第一金属侧壁，第二金属侧壁和金属底层。通过在回蚀处理中采用不均匀的保护层，第一金属侧壁的厚度小于金属底层的厚度，第二金属侧壁的厚度小于金属底层的厚度。薄的侧壁为后续的金属填充过程提供了额外的空间。

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