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1. 发明授权

US6136687A Method of forming air gaps for reducing interconnect capacitance 失效
标题翻译：形成气隙以减少互连电容的方法
公开(公告)号：US6136687A
公开(公告)日：2000-10-24
申请号：US978967
申请日：1997-11-26
申请人： Shih-Ked Lee , Chu-Tsao Yen , Cheng-Chen Calvin Hsueh , James R. Shih , Chuen-Der Lien
发明人： Shih-Ked Lee , Chu-Tsao Yen , Cheng-Chen Calvin Hsueh , James R. Shih , Chuen-Der Lien
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.
摘要翻译：制造集成电路的方法通过增加导体的有效高度来增加与电路连接的电导体部件的纵横比，通过在构图导体部件之前形成较厚的导体材料层，或者通过添加封盖电介质在图案化之前或通过过蚀刻导体部件下面的电介质材料的层。然后，该结构被具有差的阶梯覆盖的介电层覆盖，导致介电层中的空隙和开放空间的数量，从而降低图案化导体之间的介电常数。采用电介质层的等离子体回蚀来打开和形成电介质层中的附加空隙和开放空间。之后沉积第二层电介质材料以密封结构，包括第一层电介质材料中的任何开放空间。

2. 发明授权

US06489213B1 Method for manufacturing semiconductor device containing a silicon-rich layer 失效
标题翻译：含有富硅层的半导体器件的制造方法
公开(公告)号：US06489213B1
公开(公告)日：2002-12-03
申请号：US08583386
申请日：1996-01-05
申请人： Cheng-Chen Calvin Hsueh , Shih-Ked Lee
发明人： Cheng-Chen Calvin Hsueh , Shih-Ked Lee
IPC分类号： H01L2120
CPC分类号： H01L29/408 , H01L27/1112 , H01L29/513 , Y10S257/904
摘要： A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.
摘要翻译：一种具有受控电阻值在预定范围内的半导体器件。半导体器件包括衬底和设置在衬底上的氧化物层。还包括在氧化物层上方富硅的第一电介质层。还有一个在富硅层上方的第二电介质层。

3. 发明授权

US5859458A Semiconductor device containing a silicon-rich layer 失效
标题翻译：含有富硅层的半导体装置
公开(公告)号：US5859458A
公开(公告)日：1999-01-12
申请号：US652861
申请日：1996-07-16
申请人： Cheng-Chen Calvin Hsueh , Shih-Ked Lee
发明人： Cheng-Chen Calvin Hsueh , Shih-Ked Lee
IPC分类号： H01L27/11 , H01L29/06 , H01L29/40 , H01L29/51 , H01L27/01 , H01L27/12 , H01L29/94
CPC分类号： H01L29/408 , H01L27/1112 , H01L29/513 , Y10S257/904
摘要： A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.
摘要翻译：一种具有受控电阻值在预定范围内的半导体器件。半导体器件包括衬底和设置在衬底上的氧化物层。还包括在氧化物层上方富硅的第一电介质层。还有一个在富硅层上方的第二电介质层。

4. 发明授权

US07678694B2 Method for fabricating semiconductor device with silicided gate 有权
标题翻译：用硅化物栅极制造半导体器件的方法
公开(公告)号：US07678694B2
公开(公告)日：2010-03-16
申请号：US11787842
申请日：2007-04-18
申请人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
发明人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.
摘要翻译：一种用于制造半导体器件的方法，该半导体器件具有硅化物栅极，其被引导以形成硅化物结构，同时保持栅极 - 电介质完整性。最初，栅极结构优选地具有通过栅极电介质从衬底分离的多晶硅栅极，然后在至少多晶硅栅极上沉积金属层。制造环境放置在高温下。栅极结构可以是包括在诸如CMOS器件的双栅极器件中的两个栅极结构之一，在这种情况下，各个栅极可以形成在不同的高度（厚度），以确保硅化物形成适当的相位。源极和漏极区域也优选是硅化的，但是在通过例如光致抗蚀剂或硬掩模结构的盖保护栅电极的同时进行的单独工艺。

5. 发明授权

US06670247B2 Method of fabricating mask read only memory 有权
公开(公告)号：US06670247B2
公开(公告)日：2003-12-30
申请号：US09924323
申请日：2001-08-08
申请人： Cheng-Chen Calvin Hsueh
发明人： Cheng-Chen Calvin Hsueh
IPC分类号： H01L218236
CPC分类号： H01L27/1126 , H01L27/112
摘要： A method of fabricating a mask read only memory. Embedded bit line are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The word line is perpendicular to the bit lines. The substrate under the word line and between each pair of the bit lines is referred as a memory unit. A first dielectric layer is formed to cover the substrate. A plurality of coding windows is formed in the first dielectric layer over the memory units. Ions are implanted into the memory cells exposed by the coding windows, and a second dielectric layer is formed to fill the coding windows.

6. 发明申请

US20080179293A1 APPARATUS AND METHOD FOR CONTROLLING SILICON NITRIDE ETCHING TANK 有权
标题翻译：用于控制氮化硅蚀刻罐的装置和方法
公开(公告)号：US20080179293A1
公开(公告)日：2008-07-31
申请号：US11627030
申请日：2007-01-25
申请人： Zin-Chang Wei , Tsung-Min Huang , Ming-Tsao Chiang , Cheng-Chen Calvin Hsueh
发明人： Zin-Chang Wei , Tsung-Min Huang , Ming-Tsao Chiang , Cheng-Chen Calvin Hsueh
IPC分类号： B44C1/22 , H01L21/306
CPC分类号： H01L21/30604 , H01L21/31111 , H01L22/20
摘要： A method and system for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.
摘要翻译：用于控制氮化硅蚀刻槽的方法和系统提供了包括加热到高温的磷酸的蚀刻浴。控制磷酸中硅的浓度以保持与期望的氮化硅/氧化硅蚀刻选择性相关联的期望水平。测量硅浓度，同时硅保持可溶形式，并在二氧化硅沉淀之前。响应于测量，当必要时将新鲜加热的磷酸添加到蚀刻浴中以保持所需的浓度和氮化硅：氧化硅蚀刻选择性并防止二氧化硅沉淀。添加新鲜加热的磷酸使蚀刻液保持在稳态。可以使用原子吸收光谱来监测通过用冷去离子水稀释磷酸样品并在二氧化硅沉淀发生之前测量可以获得的硅浓度。

7. 发明申请

US20080032482A1 ISOLATION STRUCTURES AND METHODS OF FABRICATING ISOLATION STRUCTURES 有权
标题翻译：隔离结构和制作隔离结构的方法
公开(公告)号：US20080032482A1
公开(公告)日：2008-02-07
申请号：US11462571
申请日：2006-08-04
申请人： Cheng-Yuan Tsai , Chih-Lung Lin , Cheng-Chen Calvin Hsueh
发明人： Cheng-Yuan Tsai , Chih-Lung Lin , Cheng-Chen Calvin Hsueh
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS layer, the dielectric layer substantially filling the opening.
摘要翻译：形成隔离结构的方法包括以下步骤：（a）在衬底内形成开口; （b）沿开口形成包含四乙氧基硅烷（TEOS）层的基本上共形的层; 和（c）在TEOS层上形成介电层，介电层基本上填充开口。

8. 发明申请

US20080261394A1 Method for fabricating semiconductor device with silicided gate 有权
标题翻译：用硅化物栅极制造半导体器件的方法
公开(公告)号：US20080261394A1
公开(公告)日：2008-10-23
申请号：US11787842
申请日：2007-04-18
申请人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
发明人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
IPC分类号： H01L21/44 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.
摘要翻译：一种用于制造半导体器件的方法，该半导体器件具有硅化物栅极，其被引导以形成硅化物结构，同时保持栅极 - 电介质完整性。最初，栅极结构优选地具有通过栅极电介质从衬底分离的多晶硅栅极，然后在至少多晶硅栅极上沉积金属层。制造环境放置在高温下。栅极结构可以是包括在诸如CMOS器件的双栅极器件中的两个栅极结构之一，在这种情况下，各个栅极可以形成在不同的高度（厚度），以确保硅化物形成适当的相位。源极和漏极区域也优选是硅化的，但是在通过例如光致抗蚀剂或硬掩模结构的盖保护栅电极的同时进行的单独工艺。

9. 发明授权

US06998316B2 Method for fabricating read only memory including a first and second exposures to a photoresist layer 有权
标题翻译：一种用于制造只读存储器的方法，包括对光致抗蚀剂层的第一和第二曝光
公开(公告)号：US06998316B2
公开(公告)日：2006-02-14
申请号：US10708228
申请日：2004-02-18
申请人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
发明人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
IPC分类号： H01L21/8236 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L27/1126 , H01L27/105 , H01L27/11293 , Y10S438/949
摘要： A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.
摘要翻译：只读存储器的制造方法提供具有存储单元区域和外围电路区域的衬底。存储单元区域具有存储单元阵列，并且外围电路区域具有晶体管。在存储单元区域中形成具有多个第一开口的精确层。第一开口在存储单元阵列中的每个存储单元的沟道区之上，并且第一开口的临界尺寸相同。在基板上形成具有第二开口和第三开口的掩模层。第二开口位于预编码存储单元区域上，并且第三开口位于晶体管栅极之上。执行离子注入以对预编码存储单元区域中的存储单元进行编码，并使用精确层和掩模层作为掩模来调节晶体管的阈值电压。

10. 发明授权

US06444521B1 Method to improve nitride floating gate charge trapping for NROM flash memory device 有权
标题翻译：改善NROM闪存器件氮化物浮栅电荷捕获的方法
公开(公告)号：US06444521B1
公开(公告)日：2002-09-03
申请号：US09710421
申请日：2000-11-09
申请人： Kent Kuo-Hua Chang , Cheng-Chen Calvin Hsueh
发明人： Kent Kuo-Hua Chang , Cheng-Chen Calvin Hsueh
IPC分类号： H01L218247
CPC分类号： H01L21/28194 , H01L21/28282 , H01L29/511 , H01L29/792
摘要： A method to improve nitride floating gate charge trapping for NROM flash memory device is disclosed. The present invention uses the SiON to replace the SiN of the NROM floating gate of the prior art. This arrangement improves the endurance and the reliability of the device and also extends data retention times. The present invention also discloses the integrated processes to fabricate the NROM flash memory device. Using the processes, the steps of fabricating the NROM are efficiently reduced, and the defects caused by the cleaning steps are eliminated.
摘要翻译：公开了一种改进NROM闪存器件的氮化物浮栅电荷俘获的方法。本发明使用SiON替代现有技术的NROM浮动栅极的SiN。这种布置提高了设备的耐久性和可靠性，并且还延长了数据保留时间。本发明还公开了制造NROM闪速存储器件的集成过程。通过这些处理，可以有效地减少制造NROM的步骤，消除由清洗步骤引起的缺陷。

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