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1. 发明授权

US07895557B2 Concurrent buffering and layer assignment in integrated circuit layout 有权
标题翻译：集成电路布局中的并行缓冲和层分配
公开(公告)号：US07895557B2
公开(公告)日：2011-02-22
申请号：US12100477
申请日：2008-04-10
申请人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
发明人： Charles J. Alpert , Zhuo Li , Tuhin Mahmud , Stephen T. Quay , Paul G. Villarrubla
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/505
摘要： A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
摘要翻译：一种集成电流布局中并发缓存和层分配的方法和系统。插入缓冲器，并且每个网络的金属互连或“电线”的大小适合于由一个驱动器和一个或多个接收器组成的网络，从而可以满足定时偏移约束。如果可以通过网络的推广来修复浪费的违规行为，或者如果该促销活动可用的“松弛”收益等于或大于预先指定的促销门槛层，长网将被提升到更高的水平。响应于确定这些层分配，该方法和系统然后系统地降低不关键且不影响电路和电气约束的网，以便最小化高层线材资源的使用。

2. 发明授权

US08365120B2 Resolving global coupling timing and slew violations for buffer-dominated designs 有权
标题翻译：解决以缓冲区为主的设计的全局耦合时序和回滚冲突
公开(公告)号：US08365120B2
公开(公告)日：2013-01-29
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可路由与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

3. 发明申请

US20120144358A1 Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs 有权
标题翻译：解决缓冲区主导设计的全局耦合时序和摆动违例
公开(公告)号：US20120144358A1
公开(公告)日：2012-06-07
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Clabes G. Joachim , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可租借与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

4. 发明申请

US20130326450A1 EARLY DESIGN CYCLE OPTIMZATION 失效
标题翻译：早期设计周期优化
公开(公告)号：US20130326450A1
公开(公告)日：2013-12-05
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

5. 发明授权

US08640075B2 Early design cycle optimzation 失效
标题翻译：早期设计周期优化
公开(公告)号：US08640075B2
公开(公告)日：2014-01-28
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

6. 发明授权

US08539400B2 Routability using multiplexer structures 失效
标题翻译：使用多路复用器结构的路由性
公开(公告)号：US08539400B2
公开(公告)日：2013-09-17
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

7. 发明申请

US20120124539A1 Clock Optimization with Local Clock Buffer Control Optimization 有权
标题翻译：时钟优化与本地时钟缓冲区控制优化
公开(公告)号：US20120124539A1
公开(公告)日：2012-05-17
申请号：US12947445
申请日：2010-11-16
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.
摘要翻译：提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。物理综合工具克隆了第一个本地时钟缓冲区。然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

8. 发明申请

US20130086545A1 EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS 有权
标题翻译：基于平均全局边缘约束的评估路线约束
公开(公告)号：US20130086545A1
公开(公告)日：2013-04-04
申请号：US13252868
申请日：2011-10-04
申请人： Charles J. Alpert , Zhuo Li , Lakshmi N. Reddy , Chin Ngai Sze , Yaoguang Wei
发明人： Charles J. Alpert , Zhuo Li , Lakshmi N. Reddy , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.
摘要翻译：集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％和20％。水平和垂直的全局边缘分开处理。可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。直方图还可以与拥塞驱动的物理综合工具结合使用。

9. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

10. 发明申请

US20120324409A1 ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION 失效
标题翻译：门锁延迟计算的精度针脚模式
公开(公告)号：US20120324409A1
公开(公告)日：2012-12-20
申请号：US13162806
申请日：2011-06-17
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.
摘要翻译：通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。基于输入转换速率来计算所选择的门的延迟。输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

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