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1. 发明授权

US08640075B2 Early design cycle optimzation 失效
标题翻译：早期设计周期优化
公开(公告)号：US08640075B2
公开(公告)日：2014-01-28
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill, III , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

2. 发明申请

US20130326450A1 EARLY DESIGN CYCLE OPTIMZATION 失效
标题翻译：早期设计周期优化
公开(公告)号：US20130326450A1
公开(公告)日：2013-12-05
申请号：US13486177
申请日：2012-06-01
申请人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
发明人： Charles Jay Alpert , Robert M. Averill , Zhuo Li , Jose L. P. Neves , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译：一些示例性实施例包括用于设计集成电路的计算机实现的方法。计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。

3. 发明授权

US08443324B2 Routing and timing using layer ranges 失效
标题翻译：使用层次范围的路由和定时
公开(公告)号：US08443324B2
公开(公告)日：2013-05-14
申请号：US13047492
申请日：2011-03-14
申请人： Charles Jay Alpert , Shiyan Hu , Zhuo Li , Chin Ngai Sze
发明人： Charles Jay Alpert , Shiyan Hu , Zhuo Li , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5077
摘要： A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）的设计中使用层范围的改进路由的方法，系统和计算机程序产品。使用在数据处理系统中执行的应用程序，计算使用设计中的一组层路由的一组网络中的网络的得分。网络集合根据与网络集中的网络相关联的分数进行排序。来自一组层范围的层范围被分配给排序列表中的网，使得具有高于阈值得分的网被分配高层范围。

4. 发明授权

US07392493B2 Techniques for super fast buffer insertion 有权
标题翻译：超快速缓冲插入技术
公开(公告)号：US07392493B2
公开(公告)日：2008-06-24
申请号：US10996292
申请日：2004-11-22
申请人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
发明人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036
摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.
摘要翻译：在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。滑动分析计算插入在节点v处的给定缓冲器b的输出滑动SL（v）为SL（v）= RS（b）.C（v）+ KS（b），其中C（v）是下游电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。也可以基于信号极性来计算给定缓冲器的延迟。然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

5. 发明申请

US20140074389A1 SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING 有权
公开(公告)号：US20140074389A1
公开(公告)日：2014-03-13
申请号：US13612331
申请日：2012-09-12
申请人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G08G1/00
CPC分类号： G08G9/00 , G08G1/0104
摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.

6. 发明申请

US20130272126A1 CONGESTION AWARE ROUTING USING RANDOM POINTS 有权
标题翻译：使用随机点的约束注意事项
公开(公告)号：US20130272126A1
公开(公告)日：2013-10-17
申请号：US13445150
申请日：2012-04-12
申请人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： H04L12/24
CPC分类号： H04L41/145 , H04L45/125
摘要： In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin.
摘要翻译：在使用集成电路（IC）设计中的随机点的拥塞感知点对点路由中，随机点在IC设计的布局中定义的边界区域中选择。在边界区域中的源极引脚和引脚引脚之间构成一组模式路由，即通过随机点的模式路由集合中的模式路由。计算与该组模式路由相对应的一组拥塞成本。该拥塞成本集中的拥塞成本对应于该组模式路由中的模式路由。从一组模式路由中选择优选模式路由，优选模式路由在拥塞成本集合中具有最小拥塞成本。优选的模式路由作为源引脚和引脚引脚之间的点到点路由输出。

7. 发明授权

US08458634B2 Latch clustering with proximity to local clock buffers 失效
标题翻译：锁定聚类，靠近本地时钟缓冲区
公开(公告)号：US08458634B2
公开(公告)日：2013-06-04
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

8. 发明申请

US20130096976A1 COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK 审中-公开
标题翻译：成本有效和可靠的实用性分配网络
公开(公告)号：US20130096976A1
公开(公告)日：2013-04-18
申请号：US13275609
申请日：2011-10-18
申请人： Charles Jay Alpert , Peter Feldmann , Zhuo Li , Ying Liu , Sani Richard Nassif
发明人： Charles Jay Alpert , Peter Feldmann , Zhuo Li , Ying Liu , Sani Richard Nassif
IPC分类号： G06Q10/06
CPC分类号： G06Q10/06 , G06Q10/0631
摘要： A method, system, and computer program product for designing a cost-effective and reliable distribution network for a utility are provided in the illustrative embodiments. A graph connecting a set of consumers of the utility with a set of suppliers of the utility is reduced to form a plurality of clusters. A first network between a supplier and a subset of consumers in a first cluster in the plurality of clusters is improved, the improving adding a first connection in the first network to provide continuity of supply of the utility to the subset of consumers after a predetermined number of failures in the first network. A design is generated for a second network connecting the set of suppliers to the set of consumers, the second network including the first network after the improving, wherein the second network has a cost that is within a lower threshold and an upper threshold.
摘要翻译：在说明性实施例中提供了用于设计用于公用事业的成本有效且可靠的分配网络的方法，系统和计算机程序产品。将该实用程序的一组消费者与该公用事业的一组供应商连接的图被减少以形成多个集群。提高了在多个群集中的第一群集中的供应商和消费者子集之间的第一网络，改进了在第一网络中添加第一连接以在预定数量之后提供对消费者子集的效用的连续性的第一个网络中的故障。生成用于将供应商集合连接到消费者集合的第二网络的设计，包括第一网络在内的第二网络在改进之后，其中第二网络具有低于阈值和较高阈值的成本。

9. 发明申请

US20120110532A1 LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS 失效
标题翻译：对本地时钟缓冲器进行锁存的锁存器
公开(公告)号：US20120110532A1
公开(公告)日：2012-05-03
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

10. 发明授权

US07676780B2 Techniques for super fast buffer insertion 失效
标题翻译：超快速缓冲插入技术
公开(公告)号：US07676780B2
公开(公告)日：2010-03-09
申请号：US11947706
申请日：2007-11-29
申请人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
发明人： Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036
摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.
摘要翻译：在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。转换分析计算插入节点v的给定缓冲器b的输出转换SL（v）为SL（v）= RS（b）·C（v）+ KS（b），其中C（v）是下游电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。也可以基于信号极性来计算给定缓冲器的延迟。然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

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