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    • 1. 发明授权
    • Resolving global coupling timing and slew violations for buffer-dominated designs
    • 解决以缓冲区为主的设计的全局耦合时序和回滚冲突
    • US08365120B2
    • 2013-01-29
    • US12959029
    • 2010-12-02
    • Charles J. AlpertJoachim G. ClabesZhuo LiTuhin MahmudStephen T. Quay
    • Charles J. AlpertJoachim G. ClabesZhuo LiTuhin MahmudStephen T. Quay
    • G06F17/50
    • G06F17/5077G06F2217/84
    • A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
    • 提供了一种机制,用于在集成电路(IC)设计中解决提升或耦合时序问题和转换冲突,而不会牺牲延迟模式时序。 响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求,确定网络是否可以通过使用成本函数的多个小区中的小区可路由 与电池相关联,使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。 响应于网络能够通过耦合电容等于或低于门限路由到小区,网络被分配给小区内的至少一个轨道。 对于正在路由的新IC设计中的所有网络,生成新的IC设计。
    • 4. 发明申请
    • BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS
    • 缓冲插入减少VLSI电路中的WIRELENGTH
    • US20090013299A1
    • 2009-01-08
    • US12207498
    • 2008-09-10
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • G06F17/50
    • G06F17/509G06F2217/84
    • Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
    • 集成电路设计网络中的线长通过形成要互连的接收集群,在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少,以创建一个 跨越所有水槽的缓冲树。 缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。 提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿(除了群集中的那些宿)。 可以通过用不同的边界框检查不同对的汇,并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。
    • 5. 发明申请
    • Buffer Insertion to Reduce Wirelength in VLSI Circuits
    • 缓冲插入以减少VLSI电路中的线长度
    • US20070271543A1
    • 2007-11-22
    • US11383544
    • 2006-05-16
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • G06F17/50
    • G06F17/509G06F2217/84
    • Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
    • 集成电路设计网络中的线长通过形成要互连的接收集群,在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少,以创建一个 跨越所有水槽的缓冲树。 缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。 提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿(除了群集中的那些宿)。 可以通过用不同的边界框检查不同对的汇,并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。
    • 6. 发明授权
    • Buffer insertion to reduce wirelength in VLSI circuits
    • 缓冲器插入以减少VLSI电路中的电线长度
    • US07484199B2
    • 2009-01-27
    • US11383544
    • 2006-05-16
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • Charles J. AlpertTuhin MahmudStephen T. Quay
    • G06F17/50
    • G06F17/509G06F2217/84
    • Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
    • 集成电路设计网络中的线长通过形成要互连的接收集群,在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少,以创建一个 跨越所有水槽的缓冲树。 缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。 提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿(除了群集中的那些宿)。 可以通过用不同的边界框检查不同对的汇,并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。
    • 7. 发明授权
    • Slew constrained minimum cost buffering
    • 压缩约束最低成本缓冲
    • US07448007B2
    • 2008-11-04
    • US11457495
    • 2006-07-14
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • G06F17/50G06F9/45
    • G06F17/5045
    • A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
    • 缓冲插入技术解决了压摆约束,同时最大限度地减少了缓冲区成本。 该方法构建了汇的初始解决方案,每个都具有相关的成本,压摆和电容。 当解决方案向源传播时,将线电容和线压力加到解决方案中。 当选择缓冲器进行可能的插入时,将解决方案的电压设置为零,同时根据所选择的缓冲器增加解决方案的成本,并将电容设置为缓冲器的固有电容。 通过增加分支电容和成本,并选择最高的分支电压,合并两条相交线分支的解决方案。 解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新,并且消除由另一解决方案主导的任何解决方案。 选择具有最小成本的解决方案作为最终解决方案。
    • 8. 发明申请
    • Slew Constrained Minimum Cost Buffering
    • 压缩约束最小成本缓冲
    • US20080016479A1
    • 2008-01-17
    • US11457495
    • 2006-07-14
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • G06F17/50
    • G06F17/5045
    • A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
    • 缓冲插入技术解决了压摆约束,同时最大限度地减少了缓冲区成本。 该方法构建了汇的初始解决方案,每个都具有相关的成本,压摆和电容。 当解决方案向源传播时,将线电容和电线电弧加到溶液中。 当选择缓冲器进行可能的插入时,将解决方案的电压设置为零,同时根据所选择的缓冲器增加解决方案的成本,并将电容设置为缓冲器的固有电容。 通过增加分支电容和成本,并选择最高的分支电压,合并两条相交线分支的解决方案。 解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新,并且消除由另一解决方案主导的任何解决方案。 选择具有最小成本的解决方案作为最终解决方案。
    • 10. 发明申请
    • SLEW CONSTRAINED MINIMUM COST BUFFERING
    • SLEW约束最小成本缓冲
    • US20080295051A1
    • 2008-11-27
    • US12168153
    • 2008-07-06
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • Charles J. AlpertArvind K. KarandikarTuhin MahmudStephen T. QuayChin Ngai Sze
    • G06F17/50
    • G06F17/5045
    • A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
    • 缓冲插入技术解决了压摆约束,同时最大限度地减少了缓冲区成本。 该方法构建了汇的初始解决方案,每个都具有相关的成本,压摆和电容。 当解决方案向源传播时,将线电容和线压力加到解决方案中。 当选择缓冲器进行可能的插入时,将解决方案的电压设置为零,同时根据所选择的缓冲器增加解决方案的成本,并将电容设置为缓冲器的固有电容。 通过增加分支电容和成本,并选择最高的分支电压,合并两条相交线分支的解决方案。 解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新,并且消除由另一解决方案主导的任何解决方案。 选择具有最小成本的解决方案作为最终解决方案。