专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

2. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

3. 发明授权

US08495534B2 Post-placement cell shifting 失效
标题翻译：放置后细胞转移
公开(公告)号：US08495534B2
公开(公告)日：2013-07-23
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo D. Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh E. Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

4. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

5. 发明授权

US08347249B2 Incremental timing optimization and placement 有权
标题翻译：增量时序优化和放置
公开(公告)号：US08347249B2
公开(公告)日：2013-01-01
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

6. 发明申请

US20100257498A1 INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT 有权
标题翻译：增量时序优化和放置
公开(公告)号：US20100257498A1
公开(公告)日：2010-10-07
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

7. 发明授权

US08732468B2 Protecting hardware circuit design by secret sharing 有权
标题翻译：通过秘密共享保护硬件电路设计
公开(公告)号：US08732468B2
公开(公告)日：2014-05-20
申请号：US12720628
申请日：2010-03-09
申请人： Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov
发明人： Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov
IPC分类号： G06F21/00
CPC分类号： G06F21/85 , G06F21/70
摘要： Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
摘要翻译：技术能够通过对设备上的总线进行加密/解密来锁定和解锁基于集成电路（IC）的设备。总线可以是IC的系统总线，IC内的总线或外部输入/输出总线。在IC设计人员和构建IC的制造设施之间使用共享秘密协议。制造设备上的IC使用从IC设计者接收的唯一识别数据产生的加密密钥来加扰IC上的总线。通过加密密钥锁定IC总线，只有IC设计者才能够确定和通信解锁（例如，解扰）总线所需的适当激活密钥，从而使集成电路可用。

8. 发明申请

US20110292595A1 Liquid Cooling System for Stackable Modules in Energy-Efficient Computing Systems 有权
标题翻译：节能计算系统中可堆叠模块的液体冷却系统
公开(公告)号：US20110292595A1
公开(公告)日：2011-12-01
申请号：US12788863
申请日：2010-05-27
申请人： Wael R. El-Essawy , Thomas W. Keller, JR. , Jarrod A. Roy , Juan C. Rubio
发明人： Wael R. El-Essawy , Thomas W. Keller, JR. , Jarrod A. Roy , Juan C. Rubio
IPC分类号： G06F1/20
CPC分类号： H05K7/02 , G06F1/18 , G06F1/181 , G06F1/20 , H05K7/20
摘要： A computing system is provided. In the computing system, a plurality of modules physically arranged in a three dimensional hexadron configuration. In the computing system, the at least one module is either a liquid-tight module filled with a non-conductive liquid coolant or a module cooled with a liquid coolant circulating through cold plates mounted on electronic components. In the computing system, the liquid coolant is circulated in a closed loop by at least one pump through a plurality of hoses through at least one of a plurality of heat exchangers. In the computing system, the plurality of heat exchangers is coupled to an exterior portion of the surface of the computing system. In the computing system, the plurality of heat exchangers cool the liquid coolant through finned tubes exposed to the surrounding air.
摘要翻译：提供了一种计算系统。在计算系统中，以三维十六指肠配置物理排列的多个模块。在计算系统中，所述至少一个模块是填充有非导电液体冷却剂的液密模块或者通过冷却剂循环冷却的模块，所述冷却剂循环通过安装在电子部件上的冷板。在计算系统中，液体冷却剂通过至少一个泵通过多个软管通过多个热交换器中的至少一个在闭环中循环。在计算系统中，多个热交换器耦合到计算系统表面的外部部分。在计算系统中，多个热交换器通过暴露于周围空气的翅片管来冷却液体冷却剂。

9. 发明申请

US20100287374A1 Protecting Hardware Circuit Design by Secret Sharing 有权
标题翻译：通过秘密共享保护硬件电路设计
公开(公告)号：US20100287374A1
公开(公告)日：2010-11-11
申请号：US12720628
申请日：2010-03-09
申请人： Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov
发明人： Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov
IPC分类号： G06F21/00
CPC分类号： G06F21/85 , G06F21/70
摘要： Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
摘要翻译：技术能够通过对设备上的总线进行加密/解密来锁定和解锁基于集成电路（IC）的设备。总线可以是IC的系统总线，IC内的总线或外部输入/输出总线。在IC设计人员和构建IC的制造设施之间使用共享秘密协议。制造设备上的IC使用从IC设计者接收的唯一识别数据产生的加密密钥来加扰IC上的总线。通过加密密钥锁定IC总线，只有IC设计者才能够确定和通信解锁（例如，解扰）总线所需的适当激活密钥，从而使集成电路可用。

10. 发明授权

US08484594B2 Routing-based pin placement 失效
标题翻译：基于路由的引脚放置
公开(公告)号：US08484594B2
公开(公告)日：2013-07-09
申请号：US13005330
申请日：2011-01-12
申请人： Dorothy Kucar , Jarrod A. Roy
发明人： Dorothy Kucar , Jarrod A. Roy
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/40
摘要： A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.
摘要翻译：提供了一种用于基于路由的引脚放置的方法，并且包括接收具有连接信息和物理轮廓的分区电路的宏的逻辑描述，生成抽象形状作为引脚的通用形状的抽象以提供连接所述宏根据所述连接信息作为符合所述宏尺寸的形状，提供布线工具，所述路线工具具有将所述网路连接到所述销的所述引脚的所述抽象形状的任何部分的自由以创建路由网并且识别路由网络将物理轮廓作为引脚的选定位置交叉的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式