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1. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

2. 发明授权

US08347257B2 Detailed routability by cell placement 有权
标题翻译：细胞放置的详细路线
公开(公告)号：US08347257B2
公开(公告)日：2013-01-01
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh E. Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

3. 发明申请

US20130268908A1 VIA SELECTION IN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：通过集成电路设计中的选择
公开(公告)号：US20130268908A1
公开(公告)日：2013-10-10
申请号：US13443426
申请日：2012-04-10
申请人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
发明人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.
摘要翻译：公开了将通孔有效地实现为多级集成电路布局的解决方案。在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益多个通孔。

4. 发明授权

US08631375B2 Via selection in integrated circuit design 有权
标题翻译：通过集成电路设计中的选择
公开(公告)号：US08631375B2
公开(公告)日：2014-01-14
申请号：US13443426
申请日：2012-04-10
申请人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
发明人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.
摘要翻译：公开了将通孔有效地实现为多级集成电路布局的解决方案。在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益多个通孔。

5. 发明授权

US07496877B2 Electrostatic discharge failure avoidance through interaction between floorplanning and power routing 失效
标题翻译：通过布局规划和电源布线之间的相互作用来避免静电放电故障
公开(公告)号：US07496877B2
公开(公告)日：2009-02-24
申请号：US11202275
申请日：2005-08-11
申请人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
发明人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.
摘要翻译：描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构功率区域约束。创建这些局部电网结构的说明将传递给自动电力布线工具。

6. 发明授权

US06493859B1 Method of wiring power service terminals to a power network in a semiconductor integrated circuit 失效
标题翻译：将电力服务终端连接到半导体集成电路中的电力网络的方法
公开(公告)号：US06493859B1
公开(公告)日：2002-12-10
申请号：US09682641
申请日：2001-10-01
申请人： Scott W. Gould , Philip S. Honsinger , Andrew D. Huber , Patrick M. Ryan
发明人： Scott W. Gould , Philip S. Honsinger , Andrew D. Huber , Patrick M. Ryan
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power network into segments; creating power service terminal to segment connections based on a first set of criteria; removing selected power service terminal to segment connections based on a second set of criteria; and selecting one power service terminal to segment connection for each the power service terminal. The first criteria is includes power drop, wire length, wire size, wiring layer restrictions and the second criteria includes electro-migration, wire length and current criteria.
摘要翻译：公开了一种将电力从电力网络路由到电压岛内的一个或多个电力服务终端的方法，包括：将所述电力网络划分成段; 创建电力服务终端以基于第一组标准来分割连接; 移除所选电力服务终端以基于第二组标准来分段连接; 并选择一个电力服务终端来对每个电力服务终端进行分段连接。第一个标准包括功率下降，电线长度，电线尺寸，布线层限制，第二个标准包括电迁移，电线长度和电流标准。

7. 发明申请

US20190092742A1 INHIBITORS OF HEPATITIS B VIRUS TARGETING CAPSID ASSEMBLY 审中-公开
公开(公告)号：US20190092742A1
公开(公告)日：2019-03-28
申请号：US16144274
申请日：2018-09-27
申请人： Stefan G. Sarafianos , Zhengqiang Wang , Andrew D. Huber , Jing Tang
发明人： Stefan G. Sarafianos , Zhengqiang Wang , Andrew D. Huber , Jing Tang
IPC分类号： C07D333/38 , C07D409/12 , C07D417/12 , C07D495/04 , A61K31/381 , A61K31/506 , A61K31/18 , A61K31/5377 , A61K31/4155 , A61K31/427 , A61K31/519 , A61K31/4365 , A61P31/20
CPC分类号： C07D333/38 , A61K31/18 , A61K31/381 , A61K31/4155 , A61K31/427 , A61K31/4365 , A61K31/506 , A61K31/519 , A61K31/5377 , A61P31/20 , C07D409/12 , C07D417/12 , C07D495/04
摘要： The present invention provides novel compounds and methods for treating, preventing or inhibiting hepatitis B virus (HBV).

8. 发明授权

US06725439B1 Method of automated design and checking for ESD robustness 有权
标题翻译：自动设计和检查ESD鲁棒性的方法
公开(公告)号：US06725439B1
公开(公告)日：2004-04-20
申请号：US09678742
申请日：2000-10-04
申请人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
发明人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
摘要翻译：具有ESD稳健性的集成电路（IC）芯片和IC芯片接线的系统和方法。每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。这些限制被传播到设计中。阵列焊盘连接到位于芯片上的I / O单元。未使用或浮动焊盘可以直接或通过静电放电（ESD）保护装置连接到电源或接地线。还包括耦合在电源和接地或返回线路之间的多电源保护装置（ESDxx）。因此，布线使得ESD保护器件的导线和通孔足够宽，以提供足够的ESD保护。所有的芯片垫都提供了强大的ESD保护。然后可以验证设计。

9. 发明授权

US5519632A Automatic DCS routing for multilayer packages to minimize coupled noise 失效
标题翻译：用于多层封装的自动DCS布线，以最小化耦合噪声
公开(公告)号：US5519632A
公开(公告)日：1996-05-21
申请号：US43074
申请日：1993-04-05
申请人： Hai H. Chen , Ling-Hui Hao , Philip S. Honsinger , Andrew D. Huber , Thomas J. Lavery , Shuhui Lin
发明人： Hai H. Chen , Ling-Hui Hao , Philip S. Honsinger , Andrew D. Huber , Thomas J. Lavery , Shuhui Lin
IPC分类号： H01L21/82 , G06F17/50 , H01L23/12
CPC分类号： G06F17/5077
摘要： A routing method for differential current switch (DCS) pairs initially shortens the min/max length window for a first routed rail in order to increase the likelihood that length of the second rail will fall within the window. Next, the routing domain for the first rail is modified so that the first pin exit direction to the route is toward the second pin of the differential current switch pair. A suitable algorithm, such as a prior art mazerouter algorithm, is used to route the first rail along a path restricted to the routing domain. At each proposed via connection for connecting the first rail route from one plane to another, the program accepts the proposed via connection only if there is an available adjacent via for routing the second via. If a via for routing the second rail is not available, the proposed route for the first rail is rejected.
摘要翻译：用于差分电流开关（DCS）对的布线方法最初缩短了第一路由轨道的最小/最大长度窗口，以便增加第二轨道的长度将落入窗口内的可能性。接下来，对第一轨道的路由域进行修改，使得到路由的第一引脚出口方向朝向差动电流开关对的第二引脚。使用诸如现有技术的mazerouter算法的合适的算法来沿着限制到路由域的路径来路由第一轨。在每个提出的通路连接中，用于将第一轨道从一个平面连接到另一个平面，仅当存在用于路由第二通道的可用相邻通孔时，程序接受所提出的通路连接。如果用于路由第二条铁轨的通道不可用，则第一条铁路的建议路线被拒绝。

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