专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080295051A1 SLEW CONSTRAINED MINIMUM COST BUFFERING 有权
标题翻译： SLEW约束最小成本缓冲
公开(公告)号：US20080295051A1
公开(公告)日：2008-11-27
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

2. 发明授权

US07448007B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07448007B2
公开(公告)日：2008-11-04
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

3. 发明申请

US20080016479A1 Slew Constrained Minimum Cost Buffering 有权
标题翻译：压缩约束最小成本缓冲
公开(公告)号：US20080016479A1
公开(公告)日：2008-01-17
申请号：US11457495
申请日：2006-07-14
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和电线电弧加到溶液中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

4. 发明授权

US07890905B2 Slew constrained minimum cost buffering 有权
标题翻译：压缩约束最低成本缓冲
公开(公告)号：US07890905B2
公开(公告)日：2011-02-15
申请号：US12168153
申请日：2008-07-06
申请人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Tuhin Mahmud , Stephen T. Quay , Chin Ngai Sze
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.
摘要翻译：缓冲插入技术解决了压摆约束，同时最大限度地减少了缓冲区成本。该方法构建了汇的初始解决方案，每个都具有相关的成本，压摆和电容。当解决方案向源传播时，将线电容和线压力加到解决方案中。当选择缓冲器进行可能的插入时，将解决方案的电压设置为零，同时根据所选择的缓冲器增加解决方案的成本，并将电容设置为缓冲器的固有电容。通过增加分支电容和成本，并选择最高的分支电压，合并两条相交线分支的解决方案。解决方案集通过忽略具有大于压摆约束的转矩分量的解决方案来更新，并且消除由另一解决方案主导的任何解决方案。选择具有最小成本的解决方案作为最终解决方案。

5. 发明申请

US20070283301A1 System and Method of Eliminating Electrical Violations 审中-公开
标题翻译：消除电气违规的制度和方法
公开(公告)号：US20070283301A1
公开(公告)日：2007-12-06
申请号：US11422174
申请日：2006-06-05
申请人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
发明人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5045
摘要： A system and method for correcting electrical violations, the method including examining a plurality of nets for at least one electrical violation in a sequential order of a first output-to-input traversal, and determining a net correction in each net of the plurality of nets having an electrical violation prior to examining a next net in the sequential order of the first output-to-input traversal.
摘要翻译：一种用于校正电气违规的系统和方法，所述方法包括以第一输出到输入遍历的顺序检查多个网络中的至少一个电气违规，以及确定多个网络的每个网络中的净校正在按照第一输出到输入遍历的顺序检查下一个网络之前具有电气违规。

6. 发明申请

US20080288905A1 Method and Apparatus for Congestion Based Physical Synthesis 审中-公开
标题翻译：基于拥塞的物理综合方法与装置
公开(公告)号：US20080288905A1
公开(公告)日：2008-11-20
申请号：US11748514
申请日：2007-05-15
申请人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design.
摘要翻译：在说明性实施例中提供了用于修改电路设计的计算机实现的方法，装置和计算机可用程序产品。确定电路设计中的一组候选区域用于改变电路设计。与候选区域集合中的每个候选区域相关联的成本被确定以形成一组成本。与候选区域相关的成本是对候选区域中的电路设计进行更改的成本。使用一组成本，从对电路设计进行改变的候选区域集合中选择候选区域。

7. 发明申请

US20090089721A1 METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION 审中-公开
标题翻译：增量，时序驱动，物理综合优化的方法
公开(公告)号：US20090089721A1
公开(公告)日：2009-04-02
申请号：US11866231
申请日：2007-10-02
申请人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。具有线性评估（RUMBLE）功能的移动和移动盒识别用于定时驱动优化的可移动门。 RUMBLE实用程序隔离与可移动门对应的原始子电路，并构建原始子电路的无缓冲模型。值得注意的是，产生了可移动门的新优化布置，以优化原始子电路的定时（即，最大化最小松弛），同时考虑到将来的互连优化。评估包含新优化的栅极布局和互连优化的新子电路是否存在新的子电路中的定时劣化。如果新的子电路中存在定时降级，则RUMBLE实用程序可以恢复原始子电路和与原始子电路相关联的定时状态。

8. 发明授权

US08365120B2 Resolving global coupling timing and slew violations for buffer-dominated designs 有权
标题翻译：解决以缓冲区为主的设计的全局耦合时序和回滚冲突
公开(公告)号：US08365120B2
公开(公告)日：2013-01-29
申请号：US12959029
申请日：2010-12-02
申请人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Joachim G. Clabes , Zhuo Li , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/84
摘要： A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.
摘要翻译：提供了一种机制，用于在集成电路（IC）设计中解决提升或耦合时序问题和转换冲突，而不会牺牲延迟模式时序。响应于针对新IC设计中的多个网络中的每个网络而接收的用于生成新的IC设计的请求，确定网络是否可以通过使用成本函数的多个小区中的小区可路由与电池相关联，使得与网络相关联的耦合电容等于或低于预定的耦合电容阈值。响应于网络能够通过耦合电容等于或低于门限路由到小区，网络被分配给小区内的至少一个轨道。对于正在路由的新IC设计中的所有网络，生成新的IC设计。

9. 发明申请

US20090064080A1 BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS 审中-公开
公开(公告)号：US20090064080A1
公开(公告)日：2009-03-05
申请号：US12261027
申请日：2008-10-29
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.

10. 发明申请

US20090013299A1 BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS 审中-公开
标题翻译：缓冲插入减少VLSI电路中的WIRELENGTH
公开(公告)号：US20090013299A1
公开(公告)日：2009-01-08
申请号：US12207498
申请日：2008-09-10
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式