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1. 发明申请

US20130078815A1 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH REDUCED LINE EDGE ROUGHNESS 审中-公开
标题翻译：用减少线边缘粗糙度形成半导体结构的方法
公开(公告)号：US20130078815A1
公开(公告)日：2013-03-28
申请号：US13244013
申请日：2011-09-23
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/3065
CPC分类号： H01L21/31116 , B23K10/003 , B23K2101/40
摘要： A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency.
摘要翻译：提供了一种形成具有线边缘粗糙度降低的半导体结构的方法，包括：提供其上形成有图案化光致抗蚀剂层的器件层; 以及执行等离子体蚀刻工艺以对其上形成有图案化的光致抗蚀剂层进行图案化，形成图案化的器件层，其中等离子体蚀刻工艺在具有相对较高频率和开关的连续的阶段电压下操作脉冲调制的阶段电压具有相对较低的频率。

2. 发明申请

US20120288802A1 METHOD OF FORMING GATE CONDUCTOR STRUCTURES 有权
标题翻译：形成栅极导体结构的方法
公开(公告)号：US20120288802A1
公开(公告)日：2012-11-15
申请号：US13103108
申请日：2011-05-09
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/28132
摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
摘要翻译：一种形成栅极导体结构的方法。提供了具有栅电极层的基板。形成覆盖栅电极层的多层硬掩模。多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。在多层硬掩模上形成光刻胶图形。执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

3. 发明授权

US08758984B2 Method of forming gate conductor structures 有权
标题翻译：形成栅极导体结构的方法
公开(公告)号：US08758984B2
公开(公告)日：2014-06-24
申请号：US13103108
申请日：2011-05-09
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/70
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/28132
摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
摘要翻译：一种形成栅极导体结构的方法。提供了具有栅电极层的基板。形成覆盖栅电极层的多层硬掩模。多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。在多层硬掩模上形成光刻胶图形。执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

4. 发明申请

US20120289050A1 METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA 审中-公开
标题翻译：在利用脉冲和无氟等离子体的半导体衬底中蚀刻铁素体的方法
公开(公告)号：US20120289050A1
公开(公告)日：2012-11-15
申请号：US13103113
申请日：2011-05-09
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/3065
CPC分类号： H01L27/10844 , H01L21/3065 , H01L21/3081 , H01L21/76229
摘要： A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode.
摘要翻译：蚀刻半导体衬底中的沟槽的方法。在半导体衬底上形成图案化的硬掩模。使用图案化的硬掩模作为蚀刻掩模，然后执行等离子体蚀刻工艺以将沟槽蚀刻到未被图案化硬掩模覆盖的半导体衬底中，其中等离子体蚀刻工艺采用无碳氟化合物等离子体蚀刻化学法，并且在等离子体脉冲输出模式。

5. 发明授权

US08963282B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08963282B2
公开(公告)日：2015-02-24
申请号：US13231961
申请日：2011-09-14
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/72 , H01L23/31 , H01L23/00 , H01L21/78 , H01L21/56
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

6. 发明授权

US08692245B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08692245B2
公开(公告)日：2014-04-08
申请号：US13214227
申请日：2011-08-21
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544 , H01L23/482 , H01L21/762
CPC分类号： H01L21/76224 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
摘要翻译：本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

7. 发明授权

US08642479B2 Method for forming openings in semiconductor device 有权
标题翻译：在半导体器件中形成开口的方法
公开(公告)号：US08642479B2
公开(公告)日：2014-02-04
申请号：US13183358
申请日：2011-07-14
申请人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/32137
摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
摘要翻译：提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

8. 发明授权

US08551881B2 Method of bevel trimming three dimensional semiconductor device 有权
标题翻译：斜面修边三维半导体器件的方法
公开(公告)号：US08551881B2
公开(公告)日：2013-10-08
申请号：US13093735
申请日：2011-04-25
申请人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
发明人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/44
CPC分类号： H01L21/304 , H01L21/76898
摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.
摘要翻译：公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

9. 发明授权

US08487397B2 Method for forming self-aligned contact 有权
标题翻译：形成自对准接触的方法
公开(公告)号：US08487397B2
公开(公告)日：2013-07-16
申请号：US13093742
申请日：2011-04-25
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
摘要翻译：具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。保护屏障形成在电介质间隔物上。导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

10. 发明申请

US20130099309A1 VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE 有权
标题翻译：垂直MOSFET静电放电装置
公开(公告)号：US20130099309A1
公开(公告)日：2013-04-25
申请号：US13281293
申请日：2011-10-25
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/0266 , H01L29/0692 , H01L29/4238 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.
摘要翻译：公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域，以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

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