专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130099309A1 VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE 有权
标题翻译：垂直MOSFET静电放电装置
公开(公告)号：US20130099309A1
公开(公告)日：2013-04-25
申请号：US13281293
申请日：2011-10-25
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/0266 , H01L29/0692 , H01L29/4238 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.
摘要翻译：公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域，以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

2. 发明授权

US08367509B1 Self-aligned method for forming contact of device with reduced step height 有权
标题翻译：用于形成具有降低的台阶高度的装置的接触的自对准方法
公开(公告)号：US08367509B1
公开(公告)日：2013-02-05
申请号：US13239030
申请日：2011-09-21
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76897
摘要： A method for forming a contact of a semiconductor device with reduced step height is disclosed, comprising forming a plurality of gates, forming a buffer layer on each of the gates, forming an insulating layer to fill spaces between the gates, forming strip-shaped photoresist patterns which cross the gates, etching the insulating layer to form first openings using a self-aligning process with the gates and the strip-shaped photoresist patterns as a mask, forming a conductive contact layer to fill the first openings, performing a first chemical mechanical polish (CMP) process to the conductive contact layer, removing the buffer layer, and forming a second chemical mechanical polish (CMP) process to the conductive contact layer.
摘要翻译：公开了一种用于形成具有降低的台阶高度的半导体器件的接触的方法，包括形成多个栅极，在每个栅极上形成缓冲层，形成绝缘层以填充栅极之间的空间，形成带状光致抗蚀剂通过栅极和带状光致抗蚀剂图案作为掩模蚀刻绝缘层以形成第一开口，形成导电接触层以填充第一开口，执行第一化学机械抛光（CMP）工艺到导电接触层，去除缓冲层，以及对导电接触层形成第二化学机械抛光（CMP）工艺。

3. 发明授权

US08916003B2 Wafer scrubber 有权
标题翻译：晶圆洗涤器
公开(公告)号：US08916003B2
公开(公告)日：2014-12-23
申请号：US13243315
申请日：2011-09-23
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B3/04 , B08B17/02 , H01L21/67
CPC分类号： B08B17/025 , H01L21/67051 , H01L21/6715 , Y10S134/902
摘要： A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a meshed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the meshed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes.
摘要翻译：公开了一种晶片洗涤器，其包括腔室和连接到设置在腔室中的心轴的保持器，其中保持器支撑晶片，并且晶片旋转以去除晶片上的水，以及网状内杯，其包括多个通孔所述孔设置在所述保持器和所述室的壁之间，其中所述啮合的内杯从所述晶片的表面接收水并绕所述心轴旋转以通过所述通孔释放水。

4. 发明申请

US20130074878A1 WAFER SCRUBBER 有权
公开(公告)号：US20130074878A1
公开(公告)日：2013-03-28
申请号：US13243315
申请日：2011-09-23
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B7/00
CPC分类号： B08B17/025 , H01L21/67051 , H01L21/6715 , Y10S134/902
摘要： A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a mashed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the mashed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes.
摘要翻译：公开了一种晶片洗涤器，其包括腔室和连接到设置在腔室中的心轴的保持器，其中保持器支撑晶片，并且晶片旋转以去除晶片上的水，以及捣碎的内杯，其包括多个通孔设置在保持器和室的壁之间的孔，其中，捣碎的内杯从晶片的表面接收水并围绕心轴旋转以通过通孔释放水。

5. 发明授权

US09054131B2 Vertical MOSFET electrostatic discharge device 有权
标题翻译：垂直MOSFET静电放电装置
公开(公告)号：US09054131B2
公开(公告)日：2015-06-09
申请号：US13281293
申请日：2011-10-25
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L27/02 , H01L21/8234 , H01L29/423 , H01L29/06
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/0266 , H01L29/0692 , H01L29/4238 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.
摘要翻译：公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域，以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

6. 发明申请

US20130068264A1 WAFER SCRUBBER APPARATUS 审中-公开
公开(公告)号：US20130068264A1
公开(公告)日：2013-03-21
申请号：US13238929
申请日：2011-09-21
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B3/00
CPC分类号： H01L21/67051 , H01L21/67046
摘要： A wafer scrubber apparatus is disclosed, including a chamber, and holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and a gas purge pipe disposed at the top of a wall of the chamber, wherein the gas purge pipe comprises a plurality of gas injection holes facing downward to purge gas along the chamber wall making water flow along the chamber wall more smoothly and more quickly for preventing the water from scattering back to the wafer.
摘要翻译：公开了一种晶片洗涤器装置，包括一个腔室，以及连接到设置在腔室中的心轴的保持器，其中保持器支撑晶片，以及设置在腔室壁顶部的气体吹扫管，其中气体吹扫管包括面向下的多个气体注入孔以沿着室壁吹扫气体，使得沿着室壁的水流更顺利和更快地用于防止水散射回到晶片。

7. 发明申请

US20130078774A1 METHOD FOR FORMING DOPE REGIONS WITH RAPID THERMAL PROCESS 审中-公开
标题翻译：用快速热处理法形成区域的方法
公开(公告)号：US20130078774A1
公开(公告)日：2013-03-28
申请号：US13240931
申请日：2011-09-22
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/223 , H01L21/268 , H01L21/823814
摘要： The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate.
摘要翻译：本发明提供一种用于形成半导体器件的方法，包括提供衬底，形成栅极电介质层，在栅极电介质层上形成栅电极，在栅极电介质层和栅电极的侧壁上形成间隔物，并使用包括多个灯的快速热处理（RTP）装置和用于掺杂衬底以形成源极/漏极区域的偏置施加系统，其中在RTP装置中，气体掺杂物质被待激发的灯照射以用于转移气体掺杂剂物质与掺杂剂离子和掺杂剂离子通过来自偏置施加系统的偏压移动以掺杂到衬底中。

8. 发明授权

US08963282B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08963282B2
公开(公告)日：2015-02-24
申请号：US13231961
申请日：2011-09-14
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/72 , H01L23/31 , H01L23/00 , H01L21/78 , H01L21/56
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

9. 发明授权

US08692245B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08692245B2
公开(公告)日：2014-04-08
申请号：US13214227
申请日：2011-08-21
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544 , H01L23/482 , H01L21/762
CPC分类号： H01L21/76224 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
摘要翻译：本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

10. 发明授权

US08642479B2 Method for forming openings in semiconductor device 有权
标题翻译：在半导体器件中形成开口的方法
公开(公告)号：US08642479B2
公开(公告)日：2014-02-04
申请号：US13183358
申请日：2011-07-14
申请人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/32137
摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
摘要翻译：提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式