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1. 发明授权

US08043595B2 Mesoporous carbon including heteroatom, manufacturing method thereof, and fuel cell using the mesoporous carbon 有权
标题翻译：包含杂原子的介孔碳，其制造方法和使用介孔碳的燃料电池
公开(公告)号：US08043595B2
公开(公告)日：2011-10-25
申请号：US11443167
申请日：2006-05-31
申请人： Chan-ho Pak , Sang-hoon Joo , Hyuk Chang , Ji-man Kim , Hyung-Ik Lee
发明人： Chan-ho Pak , Sang-hoon Joo , Hyuk Chang , Ji-man Kim , Hyung-Ik Lee
IPC分类号： C01B31/00 , C01B15/12 , B01J21/18
CPC分类号： H01M4/926 , B01J21/18 , B01J23/42 , B01J29/0308 , B01J35/1061 , B01J37/0018 , B82Y30/00 , C01B32/05 , H01M4/90 , H01M4/9083 , H01M4/92
摘要： Provided are a mesoporous carbon containing at least one heteroatom boron and phosphorus, a manufacturing method thereof, and a fuel cell using the same. The mesoporous carbon contains a heteroatom such as boron and phosphorous to reduce sheet resistance, and thus can efficiently transfer electric energy. Such a mesoporous carbon can be used as a conductive material of electrodes for fuel cells. When the mesoporous carbon is used as a support for catalysts of electrodes, a supported catalyst containing the support can be used to manufacture a fuel cell having high efficiency.
摘要翻译：提供含有至少一个杂原子硼和磷的介孔碳，其制造方法和使用其的燃料电池。中孔碳含有诸如硼和磷的杂原子以降低薄层电阻，因此可以有效地转移电能。这种中孔碳可以用作燃料电池用电极的导电材料。当介孔碳用作电极催化剂的载体时，可以使用含有载体的载体催化剂来制造高效率的燃料电池。

2. 发明申请

US20090239115A1 HETEROATOM-CONTAINING MESOPOROUS CARBON, METHOD OF PREPARING THE SAME, AND FUEL CELL USING THE HETEROATOM-CONTAINING MESOPOROUS CARBON 审中-公开
标题翻译：含异构体的多孔碳，其制备方法和使用含有异质多孔碳的燃料电池
公开(公告)号：US20090239115A1
公开(公告)日：2009-09-24
申请号：US12258828
申请日：2008-10-27
申请人： Chan-ho Pak , Hyuk Chang , Ji-man Kim , Hyung-Ik Lee
发明人： Chan-ho Pak , Hyuk Chang , Ji-man Kim , Hyung-Ik Lee
IPC分类号： H01M8/10 , B32B9/00
CPC分类号： H01M4/926 , C01B32/00 , H01M4/9083
摘要： A heteroatom-containing mesoporous carbon has a pore diameter of 11 to 35 nm, has a specific surface area of 500 m2/g or more, and comprises a heteroatom. The heteroatom-containing mesoporous carbon is formed by a method including mixing a carbon precursor, a heteroatom-containing precursor, and silica particles to prepare a carbon precursor mixture; drying and carbonizing the carbon precursor mixture to prepare a silica-carbon composite; and removing silica from the silica-carbon composite. An anode and/or a cathode of fuel cell includes catalyst particles supported on the heteroatom-containing mesoporous carbon.
摘要翻译：含杂原子的介孔碳的孔径为11〜35nm，比表面积为500m 2 / g以上，且含有杂原子。通过包括混合碳前体，含杂原子的前体和二氧化硅颗粒以制备碳前体混合物的方法形成含杂原子的介孔碳; 干燥和碳化碳前体混合物以制备二氧化硅 - 碳复合材料; 并从二氧化硅 - 碳复合材料中除去二氧化硅。燃料电池的阳极和/或阴极包括负载在含杂原子的介孔碳上的催化剂颗粒。

3. 发明申请

US20120178231A1 METHODS FOR FABRICATING A METAL SILICIDE LAYER AND SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：制造金属硅化物层的方法和使用其的半导体器件
公开(公告)号：US20120178231A1
公开(公告)日：2012-07-12
申请号：US13241678
申请日：2011-09-23
申请人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
发明人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823807 , H01L21/28185 , H01L21/28518 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.
摘要翻译：提供了制造金属硅化物层和制造具有这种金属硅化物层的半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在衬底上形成金属层，在衬底上进行第一热处理，允许衬底和金属层与其它反应物反应以形成第一预金属硅化物层，去除金属层的未反应部分，并在衬底上进行第二热处理以将第一前金属硅化物层改变为第二预金属硅化物层，然后熔化第二预金属硅化物层以将第二预金属硅化物层改变为金属硅化物层。

4. 发明授权

US08294198B2 Semiconductor integrated circuit device and method of fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08294198B2
公开(公告)日：2012-10-23
申请号：US12704312
申请日：2010-02-11
申请人： Dong-Chul Yoo , Eun-Ha Lee , Byong-Ju Kim , Hyung-Ik Lee , Sung Heo , Han-Mei Choi , Chan-Hee Park , Ki-Hyun Hwang
发明人： Dong-Chul Yoo , Eun-Ha Lee , Byong-Ju Kim , Hyung-Ik Lee , Sung Heo , Han-Mei Choi , Chan-Hee Park , Ki-Hyun Hwang
IPC分类号： H01L29/72
CPC分类号： H01L29/792 , H01L21/7605 , H01L21/7607 , H01L21/76224 , H01L27/11565 , H01L27/11568 , H01L29/4234
摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.
摘要翻译：提供了一种半导体集成电路器件。半导体集成电路器件包括形成在半导体衬底内并限定有源区的多个隔离区。在每个有源区域中形成隧道层和陷阱种子层，并且依次堆叠在隔离区域之间。陷阱层形成在捕获种子层上并且比每个隔离区的顶表面更突出。在捕获层上形成阻挡层。在阻挡层上形成栅电极。

5. 发明授权

US08440527B2 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08440527B2
公开(公告)日：2013-05-14
申请号：US12659357
申请日：2010-03-05
申请人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
发明人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
IPC分类号： H01L29/788 , H01L29/792 , H01L29/66 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/02145 , H01L21/022 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L27/11521
摘要： A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.
摘要翻译：提供了一种存储器件及其制造方法。存储器件包括在衬底上的隧道电介质层，隧道电介质层上的电荷存储层，电荷存储层上的阻挡介电层，阻挡电介质层包括具有氧化硅的第一电介质层，所述第一电介质层具有硅酸铝，以及形成在所述第二电介质层上并具有氧化铝的第三电介质层和所述阻挡电介质层上的上电极。

6. 发明申请

US20120231605A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING A RECESSED CHANNEL 有权
标题翻译：制造包含通道的半导体器件的方法
公开(公告)号：US20120231605A1
公开(公告)日：2012-09-13
申请号：US13312176
申请日：2011-12-06
申请人： Young-Pil KIM , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
发明人： Young-Pil KIM , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/762
CPC分类号： H01L27/1052 , H01L21/76224 , H01L27/10876
摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
摘要翻译：一种包括形成隔离沟槽的方法; 在隔离沟槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

7. 发明申请

US20100200907A1 Semiconductor Integrated Circuit Device and Method of Fabricating the Same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20100200907A1
公开(公告)日：2010-08-12
申请号：US12704312
申请日：2010-02-11
申请人： Dong Chul Yoo , Eun-Ha Lee , Byong-Ju Kim , Hyung-Ik Lee , Sung Heo , Han-Mei Choi , Chan-Hee Park , Ki-Hyun Hwang
发明人： Dong Chul Yoo , Eun-Ha Lee , Byong-Ju Kim , Hyung-Ik Lee , Sung Heo , Han-Mei Choi , Chan-Hee Park , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L21/762 , H01L21/28
CPC分类号： H01L29/792 , H01L21/7605 , H01L21/7607 , H01L21/76224 , H01L27/11565 , H01L27/11568 , H01L29/4234
摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.
摘要翻译：提供了一种半导体集成电路器件。半导体集成电路器件包括形成在半导体衬底内并限定有源区的多个隔离区。在每个有源区域中形成隧道层和陷阱种子层，并且依次堆叠在隔离区域之间。陷阱层形成在捕获种子层上并且比每个隔离区的顶表面进一步突出。在捕获层上形成阻挡层。在阻挡层上形成栅电极。

8. 发明授权

US08835257B2 Method of fabricating semiconductor device including a recessed channel 有权
标题翻译：制造包括凹陷通道的半导体器件的方法
公开(公告)号：US08835257B2
公开(公告)日：2014-09-16
申请号：US13312176
申请日：2011-12-06
申请人： Young-Pil Kim , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
发明人： Young-Pil Kim , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/762 , H01L27/105 , H01L27/108
CPC分类号： H01L27/1052 , H01L21/76224 , H01L27/10876
摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
摘要翻译：一种包括形成隔离沟槽的方法; 在隔离槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

9. 发明申请

US20120003799A1 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers 有权
标题翻译：制造具有Si和SiGe外延层的半导体器件的方法
公开(公告)号：US20120003799A1
公开(公告)日：2012-01-05
申请号：US13137733
申请日：2011-09-08
申请人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
摘要翻译：制造半导体器件的方法可以包括在第一有源区（P沟道FET）上形成第一层，在第二有源区（N沟道FET）上形成第二层，第一和第二层包括硅锗（SiGe ）外延层，其顺序堆叠在硅（Si）外延层上，在包括暴露第一层的SiGe外延层的第一下部区域的层间绝缘膜中形成第一接触孔，在层间绝缘膜中形成第二接触孔，所述第二接触孔包括穿过第二层的SiGe外延层并暴露第二层的Si外延层的第二下部区域，在第一下部区域中形成包括锗（Ge）的第一金属硅化物膜，形成不包括第二金属硅化物膜的第二金属硅化物膜 Ge在第二下部区域同时形成第一金属硅化物膜。

10. 发明申请

US20110001183A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110001183A1
公开(公告)日：2011-01-06
申请号：US12659357
申请日：2010-03-05
申请人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
发明人： Dong-Chul Yoo , Eun-Ha Lee , Hyung-Ik Lee , Ki-Hyun Hwang , Sung Heo , Han-Mei Choi , Yong-Koo Kyoung , Byong-Ju Kim
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11568 , H01L21/02145 , H01L21/022 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L27/11521
摘要： A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.
摘要翻译：提供了一种存储器件及其制造方法。存储器件包括在衬底上的隧道电介质层，隧道电介质层上的电荷存储层，电荷存储层上的阻挡介电层，阻挡电介质层包括具有氧化硅的第一电介质层，所述第一电介质层具有硅酸铝，以及形成在所述第二电介质层上并具有氧化铝的第三电介质层和所述阻挡电介质层上的上电极。

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