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1. 发明授权

US08835257B2 Method of fabricating semiconductor device including a recessed channel 有权
标题翻译：制造包括凹陷通道的半导体器件的方法
公开(公告)号：US08835257B2
公开(公告)日：2014-09-16
申请号：US13312176
申请日：2011-12-06
申请人： Young-Pil Kim , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
发明人： Young-Pil Kim , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/762 , H01L27/105 , H01L27/108
CPC分类号： H01L27/1052 , H01L21/76224 , H01L27/10876
摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
摘要翻译：一种包括形成隔离沟槽的方法; 在隔离槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

2. 发明申请

US20120231605A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING A RECESSED CHANNEL 有权
标题翻译：制造包含通道的半导体器件的方法
公开(公告)号：US20120231605A1
公开(公告)日：2012-09-13
申请号：US13312176
申请日：2011-12-06
申请人： Young-Pil KIM , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
发明人： Young-Pil KIM , Hyung-Ik Lee , Woo-Sung Jeon , Ki-Hong Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/762
CPC分类号： H01L27/1052 , H01L21/76224 , H01L27/10876
摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
摘要翻译：一种包括形成隔离沟槽的方法; 在隔离沟槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

3. 发明申请

US20120178231A1 METHODS FOR FABRICATING A METAL SILICIDE LAYER AND SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：制造金属硅化物层的方法和使用其的半导体器件
公开(公告)号：US20120178231A1
公开(公告)日：2012-07-12
申请号：US13241678
申请日：2011-09-23
申请人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
发明人： Jin-Bum Kim , Young-Pil Kim , Hyung-Ik Lee , Ki-Hong Kim , Eun-Ha Lee , Jung-Yun Won , Benayad Anass
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823807 , H01L21/28185 , H01L21/28518 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.
摘要翻译：提供了制造金属硅化物层和制造具有这种金属硅化物层的半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在衬底上形成金属层，在衬底上进行第一热处理，允许衬底和金属层与其它反应物反应以形成第一预金属硅化物层，去除金属层的未反应部分，并在衬底上进行第二热处理以将第一前金属硅化物层改变为第二预金属硅化物层，然后熔化第二预金属硅化物层以将第二预金属硅化物层改变为金属硅化物层。

4. 发明授权

US07595246B2 Methods of manufacturing field effect transistors having elevated source/drain regions 有权
标题翻译：制造具有升高的源极/漏极区域的场效应晶体管的方法
公开(公告)号：US07595246B2
公开(公告)日：2009-09-29
申请号：US11636139
申请日：2006-12-08
申请人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
发明人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/0242 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L21/02642 , H01L21/02664 , H01L21/26513 , H01L27/10873 , H01L29/517
摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.
摘要翻译：制造场效应晶体管的方法包括在衬底上形成栅极图案。栅极间隔物形成在栅极图案的侧壁上。第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。第二个温度低于第一个温度。第一层和第二层限定升高的源/漏区。

5. 发明申请

US20070134880A1 Field effect transistors having elevated source/drain regions and methods of manufacturing the same 有权
标题翻译：具有升高的源极/漏极区域的场效应晶体管及其制造方法
公开(公告)号：US20070134880A1
公开(公告)日：2007-06-14
申请号：US11636139
申请日：2006-12-08
申请人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
发明人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/0242 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L21/02642 , H01L21/02664 , H01L21/26513 , H01L27/10873 , H01L29/517
摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.
摘要翻译：制造场效应晶体管的方法包括在衬底上形成栅极图案。栅极间隔物形成在栅极图案的侧壁上。第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。第二个温度低于第一个温度。第一和第二层限定升高的源极/漏极区域。

6. 发明授权

US08589369B2 Compression scheme for improving cache behavior in database systems 有权
公开(公告)号：US08589369B2
公开(公告)日：2013-11-19
申请号：US13360483
申请日：2012-01-27
申请人： Sang K. Cha , Ki-Hong Kim , Keun-Joo Kwon
发明人： Sang K. Cha , Ki-Hong Kim , Keun-Joo Kwon
IPC分类号： G06F17/30
CPC分类号： G06F17/30321 , G06F17/30327 , G06F17/30333 , Y10S707/99931 , Y10S707/99932 , Y10S707/99933 , Y10S707/99942
摘要： The apparatuses and methods described herein may operate to identify, from an index structure stored in memory, a reference minimum bounding shape that encloses at least one minimum bounding shape. Each of the at least one minimum bounding shape may correspond to a data object associated with a leaf node of the index structure. Coordinates of a point of the at least one minimum bounding shape may be associated with a set of first values to produce a relative representation of the at least one minimum bounding shape. The set of first values may be calculated relative to coordinates of a reference point of the reference minimum bounding shape such that each of the set of first values comprises a first number of significant bits fewer than a second number of significant bits representing a second value associated with a corresponding one of absolute coordinates of the point.

7. 发明申请

US20130044103A1 APPARATUS AND METHOD FOR DISPLAYING STEREOSCOPIC IMAGE 有权
标题翻译：用于显示立体图像的装置和方法
公开(公告)号：US20130044103A1
公开(公告)日：2013-02-21
申请号：US13474535
申请日：2012-05-17
申请人： Gun A. Lee , Ung-Yeon Yang , Yong-Wan Kim , Dong-Sik Jo , Ki-Hong Kim
发明人： Gun A. Lee , Ung-Yeon Yang , Yong-Wan Kim , Dong-Sik Jo , Ki-Hong Kim
IPC分类号： G06T15/00
CPC分类号： H04N13/346 , H04N13/383
摘要： Disclosed is an apparatus for displaying stereoscopic images. The apparatus for displaying stereoscopic images includes a stereoscopic image-generating part, a main display part, a sub-display part, and a translucent reflective structure part. The stereoscopic image-generating part splits a single image to generate a first stereoscopic image to be directly viewed by a user and a second stereoscopic image to be reflected and viewed by the user. The main display part directly displays the first stereoscopic image to a gaze of a user. The sub-display part displays the second stereoscopic image. The translucent reflective structure part reflects the second stereoscopic image displayed on the sub-display part.
摘要翻译：公开了一种显示立体图像的装置。用于显示立体图像的装置包括立体图像产生部分，主显示部分，子显示部分和半透明反射结构部分。立体图像生成部分分割单个图像以生成由用户直接观看的第一立体图像和由用户反射和观看的第二立体图像。主显示部分将第一立体图像直接显示给用户的凝视。子显示部显示第二立体图像。半透明反射结构部分反映显示在副显示部分上的第二立体图像。

8. 发明申请

US20120124010A1 COMPRESSION SCHEME FOR IMPROVING CACHE BEHAVIOR IN DATABASE SYSTEMS 有权
标题翻译：用于改进数据库系统中的缓存行为的压缩方案
公开(公告)号：US20120124010A1
公开(公告)日：2012-05-17
申请号：US13360483
申请日：2012-01-27
申请人： Sang K. Cha , Ki-Hong Kim , Keun-Joo Kwon
发明人： Sang K. Cha , Ki-Hong Kim , Keun-Joo Kwon
IPC分类号： G06F17/30
CPC分类号： G06F17/30321 , G06F17/30327 , G06F17/30333 , Y10S707/99931 , Y10S707/99932 , Y10S707/99933 , Y10S707/99942
摘要： The apparatuses and methods described herein may operate to identify, from an index structure stored in memory, a reference minimum bounding shape that encloses at least one minimum bounding shape. Each of the at least one minimum bounding shape may correspond to a data object associated with a leaf node of the index structure. Coordinates of a point of the at least one minimum bounding shape may be associated with a set of first values to produce a relative representation of the at least one minimum bounding shape. The set of first values may be calculated relative to coordinates of a reference point of the reference minimum bounding shape such that each of the set of first values comprises a first number of significant bits fewer than a second number of significant bits representing a second value associated with a corresponding one of absolute coordinates of the point.
摘要翻译：本文描述的装置和方法可以操作以从存储在存储器中的索引结构中识别包围至少一个最小边界形状的参考最小边界形状。所述至少一个最小边界形状中的每一个可对应于与所述索引结构的叶节点相关联的数据对象。所述至少一个最小边界形状的点的坐标可以与一组第一值相关联，以产生所述至少一个最小边界形状的相对表示。可以相对于参考最小限制形状的参考点的坐标来计算第一值集合，使得该组第一值中的每一个包括少于第二数量的有效位，第二数量的有效位少于表示相关联的第二值的第二数量的有效位与点的绝对坐标相对应。

9. 发明授权

US07974375B2 Linear phase detector and clock/data recovery circuit thereof 有权
标题翻译：线性相位检测器及其时钟/数据恢复电路
公开(公告)号：US07974375B2
公开(公告)日：2011-07-05
申请号：US11843785
申请日：2007-08-23
申请人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
发明人： Chul-Woo Kim , Seok-Soo Yoon , Young-Ho Kwak , In-Ho Lee , Ki-Hong Kim
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03D13/00 , H03L7/0891
摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.
摘要翻译：线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

10. 发明授权

US07964926B2 Image sensing devices including image sensor chips, image sensor package modules employing the image sensing devices, electronic products employing the image sensor package modules, and methods of fabricating the same 失效
标题翻译：包括图像传感器芯片，采用图像感测装置的图像传感器封装模块，采用图像传感器封装模块的电子产品及其制造方法的图像感测装置
公开(公告)号：US07964926B2
公开(公告)日：2011-06-21
申请号：US12137311
申请日：2008-06-11
申请人： Ki-Hong Kim
发明人： Ki-Hong Kim
IPC分类号： H01L31/00
CPC分类号： H01L27/14627 , H01L24/48 , H01L27/14636 , H01L31/02325 , H01L2224/48 , H01L2924/00014 , H01L2924/12043 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An image sensor package includes an image sensor chip, a handling substrate mounted on a front side of the image sensor chip and a through electrode disposed on a backside of the image sensor chip. The through electrode extends into the image sensor chip. Moreover, the image sensor chip includes a semiconductor substrate having a pixel region and a peripheral circuit region, a photoelectric transformation section disposed in the semiconductor substrate of the pixel region and a dielectric layer disposed on a front surface of the semiconductor substrate. The dielectric layer has a step region so that a top surface of the dielectric layer in the pixel region is lower than that of the dielectric layer in the peripheral circuit region. The image sensor chip further includes a conductive pad disposed on the dielectric layer in the peripheral circuit region and is electrically connected to the through electrode.
摘要翻译：图像传感器封装包括图像传感器芯片，安装在图像传感器芯片的前侧的处理基板和设置在图像传感器芯片的背面上的通孔。通孔延伸到图像传感器芯片中。此外，图像传感器芯片包括具有像素区域和外围电路区域的半导体衬底，设置在像素区域的半导体衬底中的光电转换部分和设置在半导体衬底的前表面上的电介质层。电介质层具有台阶区域，使得像素区域中的电介质层的顶表面比外围电路区域中的电介质层的顶表面低。图像传感器芯片还包括设置在外围电路区域中的电介质层上并与通孔电连接的导电焊盘。

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