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1. 发明申请

US20080117695A1 DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS 有权
标题翻译：多米诺SRAM阵列中不平衡读/写缓存的延迟机制
公开(公告)号：US20080117695A1
公开(公告)日：2008-05-22
申请号：US11560428
申请日：2006-11-16
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译：存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。

2. 发明申请

US20080212396A1 Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays 审中-公开
标题翻译： Domino SRAM数组中不平衡读/写路径的延迟机制
公开(公告)号：US20080212396A1
公开(公告)日：2008-09-04
申请号：US12098715
申请日：2008-04-07
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w1 and write_w1 signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_w1 signal and an output for outputting a delayed version of the write_w1 signal. The wordline signal is activated by the wordline decoder based on the read_w1 signal and the delayed write_w1 signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译：存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_w 1和write_w 1信号由字线解码器基于在下一个周期是执行读操作还是写操作生成。字线解码器包括具有用于接收write_w 1信号的输入的缓冲器和用于输出write_w 1信号的延迟版本的输出。字线信号由字线解码器基于read_w 1信号和延迟的write_w 1信号激活。这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。

3. 发明授权

US07400550B2 Delay mechanism for unbalanced read/write paths in domino SRAM arrays 有权
标题翻译：多米诺SRAM阵列中不平衡读/写路径的延迟机制
公开(公告)号：US07400550B2
公开(公告)日：2008-07-15
申请号：US11560428
申请日：2006-11-16
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Derick Gardner Behrends , George Francis Paulik
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译：存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。

4. 发明申请

US20090116298A1 APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写入性能评估的设备
公开(公告)号：US20090116298A1
公开(公告)日：2009-05-07
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

5. 发明申请

US20060087873A1 METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE 有权
标题翻译：用于CAM比较的增强比较和搜索时序的方法和寻址小区编码器
公开(公告)号：US20060087873A1
公开(公告)日：2006-04-27
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

6. 发明授权

US07035127B1 Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare 有权
标题翻译：方法和和寻址单元编码器，用于CAM比较的增强比较和搜索时序
公开(公告)号：US07035127B1
公开(公告)日：2006-04-25
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

7. 发明授权

US07788554B2 Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation 失效
标题翻译：体现在用于实现SRAM单元写入性能评估的机器可读介质中的设计结构
公开(公告)号：US07788554B2
公开(公告)日：2010-08-31
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：提供了体现在用于实现静态随机存取存储器（SRAM）单元写入性能评估的机器可读介质中的设计结构。 SRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

8. 发明授权

US07133320B2 Flood mode implementation for continuous bitline local evaluation circuit 失效
标题翻译：连续位线局部评估电路的洪水模式实现
公开(公告)号：US07133320B2
公开(公告)日：2006-11-07
申请号：US10981153
申请日：2004-11-04
申请人： Chad Allen Adams , Derick Gardner Behrends , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Ryan Charles Kivimagi
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。通过开始正常的写操作来引发洪泛模式。在新的数据值被强制进入SRAM单元之后，写入信号被切断。延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。

9. 发明授权

US07751266B2 High performance read bypass test for SRAM circuits 失效
标题翻译： SRAM电路的高性能读取旁路测试
公开(公告)号：US07751266B2
公开(公告)日：2010-07-06
申请号：US12146777
申请日：2008-06-26
申请人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。

10. 发明授权

US07768851B2 Apparatus for implementing SRAM cell write performance evaluation 失效
标题翻译：用于实现SRAM单元写入性能评估的装置
公开(公告)号：US07768851B2
公开(公告)日：2010-08-03
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

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