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1. 发明申请

US20050254585A1 Self clock generation structure for low power local clock buffering decoder 有权
标题翻译：用于低功耗本地时钟缓冲解码器的自身时钟生成结构
公开(公告)号：US20050254585A1
公开(公告)日：2005-11-17
申请号：US10845540
申请日：2004-05-13
申请人： Chad Adams , Toru Asano , Andrew Maust
发明人： Chad Adams , Toru Asano , Andrew Maust
IPC分类号： G06F1/06 , G06F1/32 , H04B14/04 , H04L27/06
CPC分类号： G06F1/32 , G06F1/06
摘要： A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.
摘要翻译：提供k-2-k解码器。在k-2-k解码器的最后阶段是多个字线驱动器。这些字线驱动器利用时钟信号将字线触发到存储器阵列。然而，随着硅晶片的组件密度的增加，时钟功耗成为一个严重的问题。为了缓解该问题，来自k-2-k解码器的第一级的信号向本地时钟缓冲器（LCB）提供允许字线驱动器触发的启动信号。启用信号减少了向字线驱动器传送的有效缓冲器和信号的数量，从而降低了功耗。

2. 发明授权

US07860172B2 Self clock generation structure for low power local clock buffering decoder 有权
标题翻译：用于低功耗本地时钟缓冲解码器的自身时钟生成结构
公开(公告)号：US07860172B2
公开(公告)日：2010-12-28
申请号：US10845540
申请日：2004-05-13
申请人： Chad Adams , Toru Asano , Andrew Maust
发明人： Chad Adams , Toru Asano , Andrew Maust
IPC分类号： H04B14/04
CPC分类号： G06F1/32 , G06F1/06
摘要： A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.
摘要翻译：提供k-to-2k解码器。在k-to-2k解码器的最后阶段是多个字线驱动器。这些字线驱动器利用时钟信号将字线触发到存储器阵列。然而，随着硅晶片的组件密度的增加，时钟功耗成为一个严重的问题。为了减轻这个问题，来自k-2k解码器的第一级的信号向本地时钟缓冲器（LCB）提供允许字线驱动器触发的启动信号。启用信号减少了向字线驱动器传送的有效缓冲器和信号的数量，从而降低了功耗。

3. 发明申请

US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array 审中-公开
标题翻译：微处理器存储器阵列的基于行的功率控制的方法和装置
公开(公告)号：US20070043895A1
公开(公告)日：2007-02-22
申请号：US11204417
申请日：2005-08-16
申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
发明人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
IPC分类号： G06F12/06 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3275 , G11C8/08 , Y02D10/128 , Y02D10/14 , Y02D10/152
摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
摘要翻译：提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。通常，微处理器阵列可以分为多个子阵列。此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。因此，省去了未使用的亚军消耗的电力。

4. 发明授权

US08040488B2 Substrate processing apparatus 有权
标题翻译：基板加工装置
公开(公告)号：US08040488B2
公开(公告)日：2011-10-18
申请号：US11294727
申请日：2005-12-06
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： G03B27/32 , G03B27/52 , G03D5/00
CPC分类号： G03F7/70991 , H01L21/67051 , H01L21/67173 , H01L21/67178
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a processing block for liquid immersion exposure processing, and an interface block. An exposure device is arranged adjacent to the interface block. The processing block for liquid immersion exposure processing comprises a coating processing group for resist cover film and a removal processing group for resist cover film. The resist cover film is formed in the processing block for liquid immersion exposure processing before the exposure processing. The resist cover film is removed in the processing block for liquid immersion exposure processing after the exposure processing.
摘要翻译：基板处理装置包括分度器块，抗反射膜处理块，抗蚀剂膜处理块，显影处理块，用于液浸曝光处理的处理块和界面块。曝光装置设置在接口块附近。用于液浸曝光处理的处理块包括用于抗蚀剂覆盖膜的涂覆处理组和抗蚀剂覆盖膜的去除处理组。在曝光处理之前，在用于液浸曝光处理的处理块中形成抗蚀剂覆盖膜。在曝光处理之后，在用于液浸曝光处理的处理块中去除抗蚀剂覆盖膜。

5. 发明申请

US20100129526A1 SUBSTRATE PROCESSING APPARATUS 审中-公开
标题翻译：基板加工设备
公开(公告)号：US20100129526A1
公开(公告)日：2010-05-27
申请号：US12698876
申请日：2010-02-02
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： B05D5/12
CPC分类号： H01L21/67034 , G03F7/38 , H01L21/67028 , H01L21/67051 , H01L21/67178 , H01L21/67207
摘要： A method of processing a substrate in a substrate processing apparatus that is arranged adjacent to an exposure device and includes first, second and third processing units, includes the steps of forming a film made of a photosensitive material on the substrate by said first processing unit before exposure processing by said exposure device. The method also includes applying drying processing to the substrate by said second processing unit after the exposure processing by said exposure device and applying development processing to the substrate by said third processing unit after the drying processing by said second processing unit
摘要翻译：一种在与曝光装置相邻并且包括第一，第二和第三处理单元的基板处理装置中处理基板的方法，包括以下步骤：在所述基板上由所述第一处理单元形成由感光材料制成的膜，曝光装置的曝光处理。该方法还包括在所述曝光装置的曝光处理之后通过所述第二处理单元对所述基板进行干燥处理，并且在所述第二处理单元进行干燥处理之后，通过所述第三处理单元对所述基板施加显影处理

6. 发明授权

US07423921B2 Method and apparatus for wordline redundancy control of memory in an information handling system 失效
标题翻译：用于信息处理系统中存储器的字线冗余控制的方法和装置
公开(公告)号：US07423921B2
公开(公告)日：2008-09-09
申请号：US11457507
申请日：2006-07-14
申请人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
摘要翻译：包括具有冗余字线的存储器阵列的存储器系统。存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

7. 发明申请

US20060147202A1 Substrate processing apparatus and substrate processing method 审中-公开
标题翻译：基板加工装置及基板处理方法
公开(公告)号：US20060147202A1
公开(公告)日：2006-07-06
申请号：US11295240
申请日：2005-12-06
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： G03D5/00
CPC分类号： G03F7/70991 , G03F7/70341
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a washing/development processing block, and an interface block. An exposure device is arranged adjacent to the interface block. A resist film is formed on a substrate by the resist film processing block. The substrate is washed and dried by the washing processing unit in the washing/development processing block before the substrate is subjected to the exposure processing by the exposure device.
摘要翻译：基板处理装置包括分度器块，防反射膜处理块，抗蚀剂膜处理块，洗涤/显影处理块和界面块。曝光装置设置在接口块附近。通过抗蚀剂膜处理块在基板上形成抗蚀剂膜。在通过曝光装置对基板进行曝光处理之前，通过洗涤处理单元在洗涤/显影处理块中洗涤和干燥基板。

8. 发明申请

US20060104635A1 Substrate processing apparatus and substrate processing method 有权
标题翻译：基板加工装置及基板处理方法
公开(公告)号：US20060104635A1
公开(公告)日：2006-05-18
申请号：US11273439
申请日：2005-11-10
申请人： Koji Kaneyama , Akihiro Hisai , Toru Asano , Hiroshi Kobayashi
发明人： Koji Kaneyama , Akihiro Hisai , Toru Asano , Hiroshi Kobayashi
IPC分类号： G03D5/00
CPC分类号： G03F7/70991 , Y10S414/135
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a resist cover film processing block, a resist cover film removal block, and an interface block. An exposure device is arranged adjacent to the interface block. A resist film is formed on a substrate in the resist film processing block. A resist cover film is formed on the resist film in the resist cover film processing block before the substrate is subjected to exposure processing by the exposure device.
摘要翻译：基板处理装置包括分度器块，抗反射膜处理块，抗蚀剂膜处理块，显影处理块，抗蚀剂覆盖膜处理块，抗蚀剂覆盖膜去除块和界面块。曝光装置设置在接口块附近。在抗蚀剂膜处理块中的基板上形成抗蚀剂膜。在通过曝光装置对基板进行曝光处理之前，在抗蚀剂覆盖膜处理块的抗蚀剂膜上形成抗蚀剂覆盖膜。

9. 发明申请

US20050264324A1 SOI sense amplifier with cross-coupled body terminal 有权
标题翻译：具有交叉耦合体端子的SOI读出放大器
公开(公告)号：US20050264324A1
公开(公告)日：2005-12-01
申请号：US10852863
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , G11C7/06 , H03F3/45 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , G11C7/065 , H03K3/356139
摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.
摘要翻译：用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少通过位线晶体管的动作将中间节点处的电压拉低。在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

10. 发明授权

US06944088B2 Apparatus and method for generating memory access signals, and memory accessed using said signals 失效
标题翻译：用于产生存储器访问信号的装置和方法，以及使用所述信号访问的存储器
公开(公告)号：US06944088B2
公开(公告)日：2005-09-13
申请号：US10262500
申请日：2002-09-30
申请人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F9/355 , G06F12/08 , G11C8/10 , G11C8/00
CPC分类号： G06F9/355 , G06F12/0895 , G11C8/10
摘要： A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals. Each of the selection signals activates a word line of the data array. A method is disclosed for producing signals for accessing a memory. Highest ordered portions of the first and second address signals are divided into multiple non-overlapping segments. An input signal (i.e., an I term) is generated for each of the segments, as is a carry signal. For each of the segments, when the corresponding carry signal is set, the corresponding I term is rotated one bit position. The I terms are produced as the signals.
摘要翻译：公开了一种和解解码器，其包括多个和预测解码器，进位发生器和多个旋转逻辑单元。每个和预解码器接收第一和第二地址信号的非重叠段的多个比特对，并且根据比特对产生输入信号。进位发生器接收第一和第二地址信号的低阶部分，并且产生每个对应于预测解码器中的不同一个的多个进位信号。每个旋转逻辑单元接收由相应的和预测码器和相应的一个进位信号产生的输入信号，根据进位信号旋转输入信号的位，并产生输入信号或旋转的输入信号作为输出信号。描述包括和解码器，最终解码块和数据阵列的存储器。最终解码块对和解码器的输出信号执行逻辑运算以产生选择信号。每个选择信号激活数据阵列的字线。公开了一种用于产生访问存储器的信号的方法。第一和第二地址信号的最高有序部分被分成多个非重叠段。对于每个段产生输入信号（即I项），进位信号也是如此。对于每个段，当相应的进位信号被设置时，对应的I项被旋转一位位置。我的条款是作为信号产生的。

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