专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6087226A Methods of forming capacitors including electrodes with hemispherical grained silicon layers on sidewalls thereof and related structures 失效
标题翻译：形成电容器的方法，其包括在其侧壁上具有半球形硅层的电极和相关结构
公开(公告)号：US6087226A
公开(公告)日：2000-07-11
申请号：US48501
申请日：1998-03-26
申请人： Young-sun Kim , Se-jin Shim , Cha-young Yoo , Young-wook Park
发明人： Young-sun Kim , Se-jin Shim , Cha-young Yoo , Young-wook Park
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8234
CPC分类号： H01L28/82 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： A method of forming an integrated circuit device includes forming a conductive layer on an integrated circuit substrate, and forming a buffer layer on the conductive layer opposite the integrated circuit substrate. The buffer layer and the conductive layer are patterned to provide a mesa structure including the patterned buffer and conductive layers. A conductive spacer is formed along a sidewall of the mesa structure, and a hemispherical grained silicon layer is formed on the conductive spacer opposite the sidewall of the mesa structure. The patterned buffer layer is then removed after the step of forming the hemispherical grained silicon layer. Related structures are also discussed.
摘要翻译：形成集成电路器件的方法包括在集成电路衬底上形成导电层，并在与集成电路衬底相对的导电层上形成缓冲层。将缓冲层和导电层图案化以提供包括图案化缓冲层和导电层的台面结构。沿着台面结构的侧壁形成导电间隔物，并且在与台面结构的侧壁相对的导电间隔物上形成半球状的硅层。然后在形成半球形颗粒硅层的步骤之后去除图案化的缓冲层。还讨论了相关结构。

2. 发明授权

US6004858A Methods of forming hemispherical grained silicon (HSG-Si) capacitor structures including protective layers 失效
标题翻译：形成包括保护层的半球形硅（HSG-Si）电容器结构的方法
公开(公告)号：US6004858A
公开(公告)日：1999-12-21
申请号：US988858
申请日：1997-12-11
申请人： Se-jin Shim , Young-sun Kim , Cha-young Yoo , Young-wook Park
发明人： Se-jin Shim , Young-sun Kim , Cha-young Yoo , Young-wook Park
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/84
摘要： A method of forming a capacitor structure includes the steps of forming a conductive layer on a microelectronic substrate, and forming a first hemispherical grained silicon layer on the conductive layer opposite the substrate. A protective layer is formed on the hemispherical grained silicon layer. The protective layer, the first hemispherical grained silicon layer, and the conductive layer are then patterned so that portions of the microelectronic substrate are exposed adjacent the patterned conductive layer. A second hemispherical grained silicon layer is formed on the surface of the protective layer opposite the first hemispherical grained silicon layer, on sidewalls of the patterned conductive layer, and on the exposed portions of the microelectronic substrate. Portions of the second hemispherical grained silicon layer are removed from the exposed portions of the microelectronic substrate, and the patterned protective layer is then removed.
摘要翻译：一种形成电容器结构的方法包括以下步骤：在微电子衬底上形成导电层，并在与衬底相对的导电层上形成第一半球晶粒硅层。在半球状粒状硅层上形成保护层。然后对保护层，第一半球形晶粒硅层和导电层进行构图，使得微电子衬底的部分暴露在图案化导电层附近。在保护层的与第一半球状粒状硅层相对的表面上，在图案化的导电层的侧壁上，以及微电子衬底的露出部分上形成第二半球状粒状硅层。从微电子衬底的暴露部分去除第二半球形硅层的一部分，然后去除图案化的保护层。

3. 发明授权

US5943570A Methods of forming capacitor electrodes containing HSG semiconductor layers therein 失效
标题翻译：形成其中包含HSG半导体层的电容器电极的方法
公开(公告)号：US5943570A
公开(公告)日：1999-08-24
申请号：US780636
申请日：1997-01-08
申请人： Young-wook Park , Young-sun Kim , Seung-hee Nam , Se-jin Shim , Cha-young Yoo , Kwan-young Oh
发明人： Young-wook Park , Young-sun Kim , Seung-hee Nam , Se-jin Shim , Cha-young Yoo , Kwan-young Oh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/82
摘要： A capacitor for a semiconductor memory device and a method for manufacturing the same are provided. A lower electrode of a capacitor according to the present invention has a structure in which a first conductive layer and a second conductive layer are sequentially deposited and an HSG is selectively formed on the surface thereof. The first conductive layer is composed of an amorphous or a polycrystalline silicon film having a low concentration of impurities. The second conductive layer is composed of an amorphous silicon film having a high concentration of impurities. According to the present invention, it is possible to obtain a desirable Cmin/Cmax ratio in the lower electrode of the capacitor having an HSG silicon layer and to prevent diffusion of impurities from the lower electrode of the capacitor.
摘要翻译：提供了一种用于半导体存储器件的电容器及其制造方法。根据本发明的电容器的下电极具有顺序地沉积第一导电层和第二导电层并且在其表面上选择性地形成HSG的结构。第一导电层由具有低浓度杂质的无定形或多晶硅膜构成。第二导电层由具有高浓度杂质的非晶硅膜构成。根据本发明，可以在具有HSG硅层的电容器的下电极中获得所需的Cmin / Cmax比，并且防止杂质从电容器的下电极扩散。

4. 发明授权

US5622889A High capacitance capacitor manufacturing method 失效
标题翻译：高容量电容器制造方法
公开(公告)号：US5622889A
公开(公告)日：1997-04-22
申请号：US591391
申请日：1996-01-25
申请人： Cha-young Yoo , Young-sun Kim , Young-wook Park , Se-jin Shim
发明人： Cha-young Yoo , Young-sun Kim , Young-wook Park , Se-jin Shim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method for manufacturing a high capacitance capacitor having an HSG film formed on a stack-structured lower storage node, includes the step of forming insulating films for protecting the HSG film. In the present invention the lower storage node and the HSG film formed thereon are not damaged during an etch-back process. The HSG film formed on the lower storage node is protected by means of the insulating films, thereby preventing a decrease in capacitor capacitance.
摘要翻译：一种制造具有形成在叠层结构的下存储节点上的HSG膜的高电容电容器的方法包括形成用于保护HSG膜的绝缘膜的步骤。在本发明中，形成在其上的下存储节点和HSG膜在回蚀处理期间不被损坏。形成在下部存储节点上的HSG膜通过绝缘膜保护，从而防止电容器电容的降低。

5. 发明授权

US6039811A Apparatus for fabricating polysilicon film for semiconductor device 失效
标题翻译：用于制造用于半导体器件的多晶硅膜的装置
公开(公告)号：US6039811A
公开(公告)日：2000-03-21
申请号：US871452
申请日：1997-06-09
申请人： Young-wook Park , Cha-young Yoo , Young-sun Kim , Seung-hee Nam
发明人： Young-wook Park , Cha-young Yoo , Young-sun Kim , Seung-hee Nam
IPC分类号： H01L21/28 , C23C16/24 , C23C16/44 , C23C16/54 , H01L21/205 , H01L21/677 , C23C16/00
CPC分类号： C23C16/54 , C23C16/24 , C23C16/4401
摘要： An apparatus for fabricating a semiconductor device having cooling jackets for preventing a gas from being exuded in a reaction chamber, thereby minimizing the generation of contaminating particles. The apparatus includes a reaction chamber having four cooling jackets respectively mounted on a first side wall adjacent to a wafer transfer chamber, a second side wall opposite to the first side wall, an upper wall and a bottom wall. A gate valve is disposed between the reaction chamber and the wafer transfer chamber and has a fifth cooling jacket. While fabricating a polysilicon film using the above apparatus, a pressure of a cassette chamber is controlled to be less than about 0.05 mtorr. Alternatively, a pressure of a cooling chamber and the wafer transfer are both controlled to be less than about 1.0 .mu.torr.
摘要翻译：一种用于制造具有用于防止气体渗透到反应室中的冷却夹套的半导体器件的装置，从而使污染颗粒的产生最小化。该装置包括具有分别安装在与晶片传送室相邻的第一侧壁上的四个冷却夹套的反应室，与第一侧壁相对的第二侧壁，上壁和底壁。闸阀设置在反应室和晶片传送室之间，并具有第五冷却套。在使用上述装置制造多晶硅膜的同时，将盒室的压力控制在小于约0.05毫托。或者，冷却室和晶片转移的压力都被控制为小于约1.0乇。

6. 发明授权

US06221742B1 Method for fabricating polysilicon film for semiconductor device 失效
标题翻译：制造半导体器件用多晶硅膜的方法
公开(公告)号：US06221742B1
公开(公告)日：2001-04-24
申请号：US09146260
申请日：1998-09-03
申请人： Young-wook Park , Cha-young Yoo , Young-sun Kim , Seung-hee Nam
发明人： Young-wook Park , Cha-young Yoo , Young-sun Kim , Seung-hee Nam
IPC分类号： H01L2120
CPC分类号： C23C16/54 , C23C16/24 , C23C16/4401
摘要： An apparatus for fabricating a semiconductor device having cooling jackets for preventing a gas from being exuded in a reaction chamber, thereby minimizing the generation of contaminating particles. The apparatus includes a reaction chamber having four cooling jackets respectively mounted on a first side wall adjacent to a wafer transfer chamber, a second side wall opposite to the first side wall, an upper wall and a bottom wall. A gate valve is disposed between the reaction chamber and the wafer transfer chamber and has a fifth cooling jacket. While fabricating a polysilicon film using the above apparatus, a pressure of a cassette chamber is controlled to be less than about 0.05 mtorr. Alternatively, a pressure of a cooling chamber and the wafer transfer are both controlled to be less than about 1.0 &mgr;torr.
摘要翻译：一种用于制造具有用于防止气体渗透到反应室中的冷却夹套的半导体器件的装置，从而使污染颗粒的产生最小化。该装置包括具有分别安装在与晶片传送室相邻的第一侧壁上的四个冷却夹套的反应室，与第一侧壁相对的第二侧壁，上壁和底壁。闸阀设置在反应室和晶片传送室之间，并具有第五冷却套。在使用上述装置制造多晶硅膜的同时，将盒室的压力控制在小于约0.05毫托。或者，冷却室和晶片转移的压力都被控制为小于约1.0倍。

7. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

8. 发明授权

US07723770B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
标题翻译：集成电路电容器，其中包含结晶抑制区的复合介电层
公开(公告)号：US07723770B2
公开(公告)日：2010-05-25
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L27/108
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

9. 发明申请

US20100117194A1 METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE 审中-公开
标题翻译：金属绝缘体 - 金属电容器，在较低的电极中具有化学障碍层
公开(公告)号：US20100117194A1
公开(公告)日：2010-05-13
申请号：US12639184
申请日：2009-12-16
申请人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
发明人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
IPC分类号： H01L29/92 , H01G4/06 , H01G4/008
CPC分类号： H01L21/7687 , H01L27/10852 , H01L28/65 , H01L28/75
摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
摘要翻译：金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。介电层位于下电极上。上电极位于与下电极相对的电介质层上。第一和第二导电层可以具有相同的厚度。化学阻挡层可以比第一和第二导电层中的每一个薄。讨论相关方法。

10. 发明授权

US08344439B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same 有权
标题翻译：集成电路电容器，其中包含结晶抑制区域的复合电介质层及其形成方法
公开(公告)号：US08344439B2
公开(公告)日：2013-01-01
申请号：US13171163
申请日：2011-06-28
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式