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1. 发明申请

US20080049498A1 Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US20080049498A1
公开(公告)日：2008-02-28
申请号：US11876093
申请日：2007-10-22
申请人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
发明人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
IPC分类号： G11C7/16
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

2. 发明申请

US20060256626A1 Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US20060256626A1
公开(公告)日：2006-11-16
申请号：US11460325
申请日：2006-07-27
申请人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
发明人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

3. 发明授权

US09165615B2 Coded differential intersymbol interference reduction 有权
标题翻译：编码差分符号间干扰减少
公开(公告)号：US09165615B2
公开(公告)日：2015-10-20
申请号：US13636515
申请日：2011-03-14
申请人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
发明人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
IPC分类号： G11C8/00 , G11C7/10 , G11C7/02
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译：编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。数据字包括L个符号。代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。

4. 发明授权

US09148156B2 Phase detection circuits and methods 有权
标题翻译：相位检测电路及方法
公开(公告)号：US09148156B2
公开(公告)日：2015-09-29
申请号：US13519302
申请日：2010-12-30
申请人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
发明人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
IPC分类号： G01R25/00 , H03D13/00 , H03L7/085 , H03L7/081
CPC分类号： H03L7/085 , G01R25/00 , H03D13/00 , H03L7/0816
摘要： A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.
摘要翻译：相位检测器电路比较第一和第二周期性输入信号的相位以产生输出信号。相位检测器包括使第一和第二周期性输入信号的两个不同组合产生第三和第四周期信号的电路。该电路使得第三周期信号基于第一周期信号和施加第一相对相移的第二周期信号的第一组合。电路使得第四周期信号基于第一周期信号和第二周期信号的第二组合，以提供不同的相对相移。相位检测器还包括比较电路，其将第三周期信号的功率的测量与第四周期信号的功率的测量进行比较，以产生相位比较输出信号。

5. 发明申请

US20070146038A1 Clock distribution network supporting low-power mode 有权
标题翻译：时钟分配网络支持低功耗模式
公开(公告)号：US20070146038A1
公开(公告)日：2007-06-28
申请号：US11318290
申请日：2005-12-22
申请人： Carl Werner , Ely Tsern
发明人： Carl Werner , Ely Tsern
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.
摘要翻译：时钟分配网络使用与同步电路（例如，PLL或DLL）相关联的第一反馈回路将本地时钟信号锁定到参考时钟信号。然后可以经由时钟网络选择性地将本地时钟信号分配给多个时钟目的地节点。可根据需要禁用时钟分配以节省电量。无论时钟分配是否启用，第一个反馈回路都处于活动状态。通过时钟网络的延迟可能由于温度和电源电压波动而漂移，这引起了分布式时钟信号中的相位误差。当启用时钟分配来补偿此漂移时，第二个反馈环路被激活。

6. 发明申请

US20060170453A1 Low latency multi-level communication interface 有权
公开(公告)号：US20060170453A1
公开(公告)日：2006-08-03
申请号：US11368012
申请日：2006-03-03
申请人： Jared Zerbe , Bruno Garlepp , Pak Chau , Kevin Donnelly , Mark Horowitz , Stefanos Sidiropoulos , Billy Garrett , Carl Werner
发明人： Jared Zerbe , Bruno Garlepp , Pak Chau , Kevin Donnelly , Mark Horowitz , Stefanos Sidiropoulos , Billy Garrett , Carl Werner
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

7. 发明申请

US20120187988A1 Signal Distribution Networks and Related Methods 有权
标题翻译：信号分配网络及相关方法
公开(公告)号：US20120187988A1
公开(公告)日：2012-07-26
申请号：US13498884
申请日：2010-10-09
申请人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
发明人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , G06F1/10 , H03L7/0802
摘要： A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.
摘要翻译：信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过传输线。可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

8. 发明授权

US07859436B2 Memory device receiver 有权
标题翻译：存储设备接收器
公开(公告)号：US07859436B2
公开(公告)日：2010-12-28
申请号：US12258285
申请日：2008-10-24
申请人： Carl Werner , Mark Horowitz , Pak Chau , Scott Best , Stefanos Sidiropoulos
发明人： Carl Werner , Mark Horowitz , Pak Chau , Scott Best , Stefanos Sidiropoulos
IPC分类号： H03M7/00
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.
摘要翻译：存储器件包括接收器，用于接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和代表在时间上比第一输入数据信号更早接收的第二信号的电压。存储器系统包括存储器控制器和一个或多个存储器设备，至少一个存储器设备或包括接收器以接收第一输入数据信号并产生对应于第一输入数据信号的输出信号和表示第二信号的电压比第一输入数据信号更早地接收。

9. 发明申请

US20070058768A1 Low jitter clock recovery circuit 有权
标题翻译：低抖动时钟恢复电路
公开(公告)号：US20070058768A1
公开(公告)日：2007-03-15
申请号：US11225559
申请日：2005-09-13
申请人： Carl Werner
发明人： Carl Werner
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

10. 发明申请

US20060242483A1 Built-in self-testing of multilevel signal interfaces 审中-公开
标题翻译：内置多电平信号接口的自检
公开(公告)号：US20060242483A1
公开(公告)日：2006-10-26
申请号：US11433409
申请日：2006-05-12
申请人： Carl Werner , Jared Zerbe , William Stonecypher
发明人： Carl Werner , Jared Zerbe , William Stonecypher
IPC分类号： G01R31/28
CPC分类号： G11C11/56 , G01R31/31715 , G11C11/22 , G11C16/04 , G11C29/00 , G11C29/50 , G11C2029/5004
摘要： Error detection mechanisms for signal interfaces, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms are provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or are coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators and mechanisms for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface, a group of interfaces or may operate with a master device that tests a plurality of interfaces by sending test signals for storage by and retrieval from one or more slave memory devices. The error detection mechanisms test memory circuits designed to communicate according to multi-PAM signals over printed circuit boards.
摘要翻译：用于信号接口的错误检测机制，包括用于测试多电平信号接口的内置自检（BIST）机制。误差检测机构提供在集成电路（IC）芯片中，该集成电路（IC）芯片包含至少一个信号接口或耦合到印刷电路板（PCB）上的接口。 BIST机制可以包括例如测试信号发生器和用于确定生成的测试信号是否被接口准确地发送和接收的机制。 BIST机制可以检查单个输入/输出接口，一组接口，或者可以通过发送用于由一个或多个从属存储器设备存储和检索的测试信号来测试多个接口的主设备进行操作。错误检测机构根据印刷电路板上的多PAM信号测试设计用于通信的存储器电路。

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