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1. 发明授权

US08610474B2 Signal distribution networks and related methods 有权
公开(公告)号：US08610474B2
公开(公告)日：2013-12-17
申请号：US13498884
申请日：2010-10-09
申请人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
发明人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , G06F1/10 , H03L7/0802
摘要： A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

2. 发明申请

US20120187988A1 Signal Distribution Networks and Related Methods 有权
标题翻译：信号分配网络及相关方法
公开(公告)号：US20120187988A1
公开(公告)日：2012-07-26
申请号：US13498884
申请日：2010-10-09
申请人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
发明人： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , G06F1/10 , H03L7/0802
摘要： A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.
摘要翻译：信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过传输线。可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

3. 发明申请

US20120218001A1 Techniques for Phase Detection 审中-公开
标题翻译：相位检测技术
公开(公告)号：US20120218001A1
公开(公告)日：2012-08-30
申请号：US13505714
申请日：2010-10-31
申请人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
发明人： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
IPC分类号： H03D13/00
CPC分类号： H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
摘要翻译：相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。输入信号基于两个周期信号。相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。相位比较信号响应于相位检测器的相位输入信号具有非零值。输入信号基于周期信号。输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

4. 发明申请

US20120306538A1 Phase Detection Circuits and Methods 有权
标题翻译：相位检测电路和方法
公开(公告)号：US20120306538A1
公开(公告)日：2012-12-06
申请号：US13519302
申请日：2010-12-30
申请人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
发明人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
IPC分类号： H03L7/085 , H03D13/00
CPC分类号： H03L7/085 , G01R25/00 , H03D13/00 , H03L7/0816
摘要： A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.
摘要翻译：相位检测器电路比较第一和第二周期性输入信号的相位以产生输出信号。相位检测器包括使第一和第二周期性输入信号的两个不同组合产生第三和第四周期信号的电路。该电路使得第三周期信号基于第一周期信号和施加第一相对相移的第二周期信号的第一组合。电路使得第四周期信号基于第一周期信号和第二周期信号的第二组合，以提供不同的相对相移。相位检测器还包括比较电路，其将第三周期信号的功率的测量与第四周期信号的功率的测量进行比较，以产生相位比较输出信号。

5. 发明授权

US09148156B2 Phase detection circuits and methods 有权
标题翻译：相位检测电路及方法
公开(公告)号：US09148156B2
公开(公告)日：2015-09-29
申请号：US13519302
申请日：2010-12-30
申请人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
发明人： Farshid Aryanfar , Hae-Chang Lee , Carl Werner
IPC分类号： G01R25/00 , H03D13/00 , H03L7/085 , H03L7/081
CPC分类号： H03L7/085 , G01R25/00 , H03D13/00 , H03L7/0816
摘要： A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.
摘要翻译：相位检测器电路比较第一和第二周期性输入信号的相位以产生输出信号。相位检测器包括使第一和第二周期性输入信号的两个不同组合产生第三和第四周期信号的电路。该电路使得第三周期信号基于第一周期信号和施加第一相对相移的第二周期信号的第一组合。电路使得第四周期信号基于第一周期信号和第二周期信号的第二组合，以提供不同的相对相移。相位检测器还包括比较电路，其将第三周期信号的功率的测量与第四周期信号的功率的测量进行比较，以产生相位比较输出信号。

6. 发明授权

US09425505B2 Integrated phase-shifting-and-combining circuitry to support multiple antennas 有权
标题翻译：集成的相移和组合电路支持多个天线
公开(公告)号：US09425505B2
公开(公告)日：2016-08-23
申请号：US13988047
申请日：2011-10-31
申请人： Lingkai Kong , Farshid Aryanfar
发明人： Lingkai Kong , Farshid Aryanfar
IPC分类号： H01Q3/22 , H01Q3/26 , H04B7/08
CPC分类号： H01Q3/2694 , H01Q3/26 , H01Q3/2682 , H04B7/084
摘要： The disclosed embodiments generally relate to techniques for processing signals received from multiple antennas. More specifically, the disclosed embodiments relate to a system that uses an integrated phase-shifting-and-combining circuit to process signals received from multiple antenna elements. This circuit applies a specified phase shift to the input signals, and combines the phase-shifted input signals to produce an output signal. In some embodiments, the integrated phase-shifting-and-combining circuit uses a current-steering mechanism to perform the phase-shifting-and-combining operations. This current-steering mechanism operates by converting the input signals into associated currents, and then steering each of the associated currents through multiple pathways which have different delays. Next, the currents from the multiple pathways for the associated currents are combined to produce the output signal. During this process, while steering each of the associated currents through multiple pathways to achieve different phase shifts, complementary impedance changes through the multiple pathways cause the aggregate impedance at the output to remain substantially constant.
摘要翻译：所公开的实施例通常涉及用于处理从多个天线接收的信号的技术。更具体地，所公开的实施例涉及使用集成的相移和组合电路来处理从多个天线元件接收的信号的系统。该电路对输入信号施加规定的相移，并组合移相输入信号以产生输出信号。在一些实施例中，集成的相移和组合电路使用电流导引机构来执行相移和组合操作。该电流导向机构通过将输入信号转换为相关联的电流来操作，然后通过具有不同延迟的多个路径来引导每个相关联的电流。接下来，来自相关电流的多路径的电流被组合以产生输出信号。在该过程中，当通过多个通路来引导每个相关联的电流以实现不同的相移时，通过多个通路的互补阻抗变化导致输出端的总阻抗保持基本恒定。

7. 发明授权

US09160346B2 Area and power efficient clock generation 有权
标题翻译：区域和功率有效的时钟产生
公开(公告)号：US09160346B2
公开(公告)日：2015-10-13
申请号：US14002267
申请日：2012-02-07
申请人： Vijay Khawshe , Farshid Aryanfar
发明人： Vijay Khawshe , Farshid Aryanfar
IPC分类号： G11C8/18 , H03L7/08 , G11C5/00 , G11C5/06 , G06F1/04 , G06F1/10 , H03L7/099 , G11C7/22
CPC分类号： H03L7/08 , G06F1/04 , G06F1/10 , G11C5/005 , G11C5/06 , G11C7/222 , G11C8/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2924/15311 , H01L2924/19103 , H01L2924/19104 , H03L7/099
摘要： Die-to-die interconnect structures are leveraged to form the inductive component of an LC oscillator, thus yielding an LC tank distributed across multiple IC dies rather than lumped in a single die. By this arrangement, reliance on area/power-consuming on-chip inductors may be reduced or eliminated, and phase-aligned clocks may be extracted from the LC tank within each of the spanned IC dies, obviating multiple oscillator instances or complex phase alignment circuitry.
摘要翻译：芯片间的互连结构被利用以形成LC振荡器的电感分量，从而产生分布在多个IC芯片上的LC箱，而不是集中在单个管芯中。通过这种布置，可以减少或消除对面积/功耗的片上电感器的依赖，并且可以从每个跨接的IC管芯内的LC箱中提取相位对准的时钟，消除多个振荡器实例或复相位对准电路。

8. 发明授权

US08854091B2 Integrated circuit comprising fractional clock multiplication circuitry 有权
$Integrated circuit comprising fractional clock multiplication circuitry$
标题翻译：集成电路包括分数时钟乘法电路
公开(公告)号：US08854091B2
公开(公告)日：2014-10-07
申请号：US13686175
申请日：2012-11-27
申请人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
IPC分类号： H03B19/00 , H03K3/03 , H03K5/00
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
摘要翻译：描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位进入国际劳工组织。

9. 发明申请

US20120289338A1 DIRECTIONAL BEAM STEERING SYSTEM AND METHOD TO DETECT LOCATION AND MOTION 有权
标题翻译：方向光束转向系统和检测位置和运动的方法
公开(公告)号：US20120289338A1
公开(公告)日：2012-11-15
申请号：US13574586
申请日：2011-01-13
申请人： Yu Ju Chen , Farshid Aryanfar , Carl W. Werner
发明人： Yu Ju Chen , Farshid Aryanfar , Carl W. Werner
IPC分类号： A63F9/24
CPC分类号： A63F13/235 , A63F13/213 , A63F13/843 , A63F2300/1006 , A63F2300/1031 , A63F2300/403 , A63F2300/8088 , G06F3/0346 , G06F3/038 , G06F2203/0384
摘要： A gaming system is disclosed comprising a console unit having a processor and transceiver circuitry. The transceiver circuitry couples to the processor and includes respective receiver and transmitter circuits. A first phased array antenna interface is employed to transmit and receive directional signals in response to the processor. The system employs a mobile game controller including a second phased array antenna interface to receive and redirect the directional signals back to the first phased array antenna interface. The processor generates proximity data based at least in part on a parameter associated with the directional signals, the proximity data representing the proximity of the mobile game controller with respect to the game console unit.
摘要翻译：公开了一种游戏系统，包括具有处理器和收发器电路的控制台单元。收发器电路耦合到处理器并且包括相应的接收器和发射器电路。采用第一相控阵天线接口来响应于处理器发送和接收定向信号。该系统采用包括第二相控阵天线接口的移动游戏控制器，以将定向信号接收并重定向到第一相控阵天线接口。处理器至少部分地基于与方向信号相关联的参数产生接近数据，邻近数据表示移动游戏控制器相对于游戏控制台单元的接近度。

10. 发明申请

US20110228864A1 RESONANCE MITIGATION FOR HIGH-SPEED SIGNALING 有权
标题翻译：高速信号共振减速
公开(公告)号：US20110228864A1
公开(公告)日：2011-09-22
申请号：US13129998
申请日：2009-12-03
申请人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
发明人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/00
CPC分类号： H04L25/0272 , H04L25/03878
摘要： The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link.
摘要翻译：差分信号链路的第一分量信号路径的频率响应被调整为在差分信令链路的第二分量信号路径的频率响应中的对应的陷波中使得频率响应中的陷波偏移。

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