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1. 发明授权

US06822519B1 Synthesizer structures and alignment methods that facilitate quadrature demodulation 有权
标题翻译：合成器结构和对准方法，促进正交解调
公开(公告)号：US06822519B1
公开(公告)日：2004-11-23
申请号：US10364162
申请日：2003-02-10
申请人： Carl W. Moreland , Bryan S. Puckett
发明人： Carl W. Moreland , Bryan S. Puckett
IPC分类号： H03L700
CPC分类号： H03J1/005 , H03D7/165 , H03J2200/03 , H03L7/099 , H03L7/18 , H03L7/199
摘要： Synthesizer structures and alignment methods are provided that facilitate quadrature demodulation. The structures are realized with phase-locked loops that include half-rate frequency dividers to provide loop output signals with a wide range of output frequencies and with frequency dividers that provide quadrature signals in response to the output signals. The structures include controllers that direct alignment methods which lock a VCO to a reference signal from a reference frequency divider to thereby provide the output signals.
摘要翻译：提供了促进正交解调的合成器结构和对准方法。这些结构通过包括半速率分频器的锁相环实现，以提供具有宽范围输出频率的环路输出信号，以及响应于输出信号提供正交信号的分频器。这些结构包括控制器，其将对准方法引导到将参考信号从参考分频器锁定，从而提供输出信号。

2. 发明授权

US06753732B1 Accurate, wide-band, low-noise variable-gain amplifier structures and gain control methods 有权
标题翻译：精确，宽带，低噪声可变增益放大器结构和增益控制方法
公开(公告)号：US06753732B1
公开(公告)日：2004-06-22
申请号：US10364163
申请日：2003-02-10
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F3/45089 , H03F3/45506 , H03F3/45511 , H03F2203/45362 , H03F2203/45508 , H03F2203/45642 , H03F2203/45651 , H03F2203/45694 , H03F2203/45722 , H03G1/0023 , H03G3/001
摘要： Variable-gain amplifiers (VGAs) are provided that realize gain accuracy (e.g., over variations in temperature and fabrication processes) while also providing this accuracy over a wide bandwidth and without the signal-to-noise degradation typically associated with signal attentuating elements. Differential signal and gain amplifiers of these VGAs include current sources which are controlled by a common error signal Serr. The gain amplifier is supplemented by feedback structure that generates the error signal Serr and controls the amplifier's transconductance to be the ratio of at least one of currents and resistors. Because such ratios can be well matched (especially in integrated circuit realizations of the variable-gain amplifiers) and because the current source of the signal amplifier is also controlled by the error signal Serr, this wide-band, low-noise open-loop amplifier's gain is accurately controlled.
摘要翻译：提供了可变增益放大器（VGA），其实现增益精度（例如，在温度和制造工艺上的变化），同时还可以在宽带宽上提供该精度，而不会通常与信号注意元件相关联的信噪比降低。这些VGA的差分信号和增益放大器包括由公共误差信号Serr控制的电流源。增益放大器由产生误差信号Serr的反馈结构补充，并将放大器的跨导控制为电流和电阻中至少一个的比例。因为这样的比率可以很好地匹配（特别是在可变增益放大器的集成电路实现中），并且由于信号放大器的电流源也由误差信号Serr控制，所以该宽带低噪声开环放大器增益准确控制。

3. 发明授权

US6163290A Linearizing structures and methods for unity-gain folding amplifiers 有权
标题翻译：用于单位增益折叠放大器的线性化结构和方法
公开(公告)号：US6163290A
公开(公告)日：2000-12-19
申请号：US352829
申请日：1999-07-13
申请人： Carl W. Moreland , Michael R. Elliott
发明人： Carl W. Moreland , Michael R. Elliott
IPC分类号： H03F3/45 , H03M1/44 , H03M1/12
CPC分类号： H03F3/45071 , H03F3/45479 , H03F2203/45091 , H03M1/445
摘要： Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity. The correction voltage is inserted in one of the input paths in a feedback mode of the invention and in one of the output paths in a feed-forward mode and the correction voltage is oriented to correct variations in the offset voltages of one of the differential pairs that occur adjacent a polarity transition of the differential input voltage. In serial arrangements of these amplifiers, their high linearity enhances the quantization processes of successive stages so that longer serial arrangements can be reliably used.
摘要翻译：线性化单位增益折叠放大器包括在控制端子和第一电流端子之间具有偏移电压的第一和第二差分对晶体管。控制端子通过输入路径差分耦合到差分输入端口，并且接合的第一电流端子通过相应的第一和第二电平移位电阻器接收相应的第一和第二电流。因此，折叠和电平移位的信号可以经由第一和第二电平移位电阻器和输出端口之间的输出路径进行差分耦合。对于每个差分对，当差分输入电压具有一个极性时，产生至少一个校正电压以使该差分对的晶体管的偏移电压基本匹配，当差分输入电压具有不同的极性。校正电压以本发明的反馈模式插入到一个输入路径中，并且在前馈模式中的一个输出路径中，并且校正电压被定向以校正一个差分对的偏移电压的变化其发生在差分输入电压的极性转变附近。在这些放大器的串联布置中，它们的高线性度增强了连续级的量化处理，使得可以可靠地使用更长的串行布置。

4. 发明授权

US5757220A Digitally controlled programmable attenuator 失效
标题翻译：数字控制可编程衰减器
公开(公告)号：US5757220A
公开(公告)日：1998-05-26
申请号：US772359
申请日：1996-12-23
申请人： Franklin M. Murden , Carl W. Moreland
发明人： Franklin M. Murden , Carl W. Moreland
IPC分类号： H03G1/00 , H03H11/24 , H03G3/00
CPC分类号： H03H11/24 , H03G1/0088
摘要： A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized. The buffers can be implemented with complementary bipolar or BiCMOS processes
摘要翻译：数字控制的可编程衰减器在广泛的频率范围和功率水平上保持衰减信号之间的紧密相位匹配，而不管选择的衰减水平如何。这是通过设置所需的分接头分贝dB步长的多抽头梯形网络来实现的，多个单位增益数字切换的电压 - 电压缓冲器连接在各个抽头和公共输出之间，以及一个固定增益级，用于设置衰减器的总增益/衰减。缓冲器保持高且基本恒定的阻抗，无论是开启还是关闭。实现了对于30dB的增益变化，频率高达300MHz的0.2°以内的相位匹配。缓冲区可以用互补双极或BiCMOS工艺来实现

5. 发明授权

US09207315B1 Metal detector with motion sensing 有权
标题翻译：带有运动感应的金属探测器
公开(公告)号：US09207315B1
公开(公告)日：2015-12-08
申请号：US13169427
申请日：2011-06-27
申请人： John W. Plautz , Kelly M. Plautz , Anne E. Kelley , Jeffrey L. Kelley , Carl W. Moreland
发明人： John W. Plautz , Anne E. Kelley , Jeffrey L. Kelley , Carl W. Moreland
IPC分类号： G08B21/00 , G08B13/24 , G08B13/26 , G01V3/08 , G01V3/10 , G01S13/88
CPC分类号： G01S13/885 , G01S13/887 , G01V3/10 , G01V3/101 , G01V3/104 , G01V3/15
摘要： A metal detector has a motion sensor such as an accelerometer to determine direction, speed, duration and acceleration of search loop motion. The search loop motion information from the motion sensor is utilized in mode selection, signal processing, target analysis, and information display.
摘要翻译：金属探测器具有诸如加速度计的运动传感器，以确定搜索循环运动的方向，速度，持续时间和加速度。来自运动传感器的搜索循环运动信息用于模式选择，信号处理，目标分析和信息显示。

6. 发明授权

US5861831A Intermediate frequency (IF) sampling clock-to-clock auto-ranging analog-to-digital converter (ADC) and method 失效
标题翻译：中频（IF）采样时钟到时钟自动量程模数转换器（ADC）和方法
公开(公告)号：US5861831A
公开(公告)日：1999-01-19
申请号：US772358
申请日：1996-12-23
申请人： Franklin M. Murden , Carl W. Moreland , Harvey J. Ray , Michael R. Elliott , Marvin J. Young
发明人： Franklin M. Murden , Carl W. Moreland , Harvey J. Ray , Michael R. Elliott , Marvin J. Young
IPC分类号： H03M1/18 , H03M1/62
CPC分类号： H03M1/186
摘要： A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.
摘要翻译：时钟到时钟自动量程ADC直接在IF频带或更高的模拟信号上进行操作，以便在时钟基础上跟踪其增益范围，并产生数字信号，保持模拟信号的高分辨率，无需剪辑或信号灵敏度损失。这通过对具有足够高频率的模拟信号进行采样来实现，峰值检测器可以在至少半个信号周期上精确地确定最大信号电平，然后在下一个采样开始之前复位进入ADC的信号增益期。这确保模拟信号始终在ADC的范围内。根据众所周知的抽样原理，采样模拟信号被混叠到DC与采样频率的一半之间的频率区域。

7. 发明授权

US5539338A Input or output selectable circuit pin 失效
标题翻译：输入或输出可选电路引脚
公开(公告)号：US5539338A
公开(公告)日：1996-07-23
申请号：US348052
申请日：1994-12-01
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03K19/173 , H03K5/19
CPC分类号： H03K19/1732
摘要： A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.
摘要翻译：用于在两个状态之间选择并使用与输入和输出相同的引脚的电路。上电时，引脚可以连接到接地电阻（选择第一个状态）或电源（选择第二个状态）。输入信号产生逻辑选择信号。逻辑选择信号在第一和第二逻辑格式之间进行选择。如果选择了第一种格式，该引脚用于输出该格式的参考电压。如果选择了第二种格式，逻辑选择信号也提供一个禁止信号，可以防止参考电压输出出现在引脚上。

8. 发明授权

US06686864B1 Pipelined analog-to-digital converters with gain-matching structures 有权
标题翻译：具有增益匹配结构的流水线模数转换器
公开(公告)号：US06686864B1
公开(公告)日：2004-02-03
申请号：US10229039
申请日：2002-08-28
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03M138
CPC分类号： H03M1/0604 , H03M1/167
摘要： Pipelined ADC systems are provided with gain-matching structures that substantially eliminate gain errors between preceding and succeeding converter stages. These structures include reference signal-conditioning elements which mimic at least one of main signal-conditioning elements in the succeeding converter stages. The reference signal-conditioning elements control reference signals which maintain a match between the full-scale range of a digital-to-analog converter (DAC) in a succeeding stage and the “gained-up” step size of a DAC in a preceding stage. This match substantially eliminates the gain errors.
摘要翻译：流水线ADC系统提供增益匹配结构，基本上消除了前一个和后一个转换器级之间的增益误差。这些结构包括模拟后续转换器级中的主信号调节元件中的至少一个的参考信号调节元件。参考信号调理元件控制参考信号，其保持后级中的数模转换器（DAC）的满量程范围与前一级中的DAC的“增大”步长之间的匹配。该匹配基本上消除了增益误差。

9. 发明授权

US06307491B1 Trim systems and methods having temporary and permanent operational modes 有权
标题翻译：修剪系统和方法具有临时和永久的操作模式
公开(公告)号：US06307491B1
公开(公告)日：2001-10-23
申请号：US09512730
申请日：2000-02-24
申请人： Carl W. Moreland , Russel G. Stop
发明人： Carl W. Moreland , Russel G. Stop
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/46 , H03M1/745 , H03M1/785
摘要： Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.
摘要翻译：锁存系统和方法被配置为在设定和复位状态的实验组合中临时锁存微调信号，并且随后以优选组合（即，优化电子电路的性能参数的组合）永久地锁存微调信号。本发明的闩锁系统包括闩锁，复位驱动器，临时设置驱动器和永久设置驱动器，并且特别适用于在永久锁定该优选组合之前确定设置和复位状态的优选组合。

10. 发明授权

US06294902B1 Bandgap reference having power supply ripple rejection 有权
标题翻译：具有电源纹波抑制的带隙基准
公开(公告)号：US06294902B1
公开(公告)日：2001-09-25
申请号：US09637807
申请日：2000-08-11
申请人： Carl W. Moreland , Marvin J. Young
发明人： Carl W. Moreland , Marvin J. Young
IPC分类号： G05F140
CPC分类号： G05F3/30
摘要： A bandgap reference circuit provides an output reference voltage that is generally insensitive to fluctuations in supply voltage, ambient temperature, and output load current. A current regulator establishes an output whose variations are reduced, preferably logarithmically, relative to variations in a supply voltage. A bandgap generator fed by the output current provides an output reference voltage with similarly suppressed variations. A control amplifier biases the bandgap generator to provide a high level common-mode rejection of various error sources.
摘要翻译：带隙参考电路提供对电源电压，环境温度和输出负载电流波动通常不敏感的输出参考电压。电流调节器建立相对于电源电压变化优选对数减小的输出。由输出电流馈送的带隙发生器提供具有类似抑制变化的输出参考电压。控制放大器偏置带隙发生器以提供各种误差源的高电平共模抑制。

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