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1. 发明授权

US07173470B2 Clock sources and methods with reduced clock jitter 有权
标题翻译：时钟源和减少时钟抖动的方法
公开(公告)号：US07173470B2
公开(公告)日：2007-02-06
申请号：US11078272
申请日：2005-03-11
申请人： Franklin M. Murden , Ahmed Mohamed Abdelatty Ali
发明人： Franklin M. Murden , Ahmed Mohamed Abdelatty Ali
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.
摘要翻译：提供的时钟源对于减少信号采样器中的相位噪声特别有用，通常在诸如模数转换器的信号调节系统中提供模拟输入信号的采样。通过识别出采样器噪声与输入信号的转换速率与时钟转换速率的比值与时钟抖动有关，实现了该相位降噪。时钟实施例包括分频器和信号门。分频器分割第一信号以提供具有从第一信号的转换速率降低的转换速率的第二信号，并且当由第一信号命令时门通过第二信号从而产生时钟信号。

2. 发明授权

US5757220A Digitally controlled programmable attenuator 失效
标题翻译：数字控制可编程衰减器
公开(公告)号：US5757220A
公开(公告)日：1998-05-26
申请号：US772359
申请日：1996-12-23
申请人： Franklin M. Murden , Carl W. Moreland
发明人： Franklin M. Murden , Carl W. Moreland
IPC分类号： H03G1/00 , H03H11/24 , H03G3/00
CPC分类号： H03H11/24 , H03G1/0088
摘要： A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized. The buffers can be implemented with complementary bipolar or BiCMOS processes
摘要翻译：数字控制的可编程衰减器在广泛的频率范围和功率水平上保持衰减信号之间的紧密相位匹配，而不管选择的衰减水平如何。这是通过设置所需的分接头分贝dB步长的多抽头梯形网络来实现的，多个单位增益数字切换的电压 - 电压缓冲器连接在各个抽头和公共输出之间，以及一个固定增益级，用于设置衰减器的总增益/衰减。缓冲器保持高且基本恒定的阻抗，无论是开启还是关闭。实现了对于30dB的增益变化，频率高达300MHz的0.2°以内的相位匹配。缓冲区可以用互补双极或BiCMOS工艺来实现

3. 发明授权

US07623051B2 Metastability error reduction in signal converter systems 有权
标题翻译：信号转换器系统的易变性误差降低
公开(公告)号：US07623051B2
公开(公告)日：2009-11-24
申请号：US12150659
申请日：2008-04-29
申请人： Franklin M. Murden , Michael R. Elliott
发明人： Franklin M. Murden , Michael R. Elliott
IPC分类号： H03M1/10
CPC分类号： H03M1/0809 , H03M1/068 , H03M1/069 , H03M1/0863 , H03M1/164
摘要： Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.
摘要翻译：提供了信号转换器系统，其减少了当模拟输入信号接近系统比较器的参考阈值Vth时通常发生的亚稳转换误差引起的系统误码率的降低。当操作正确时，当输入信号越过阈值时，比较器产生相应的转换器代码。然而，可调节性可能会导致比较器无法生成相应的转换器代码。在系统实施例中，提供逻辑以在预定判定周期结束时感测到不存在比较器判定。响应于这种缺失，系统被配置为替换相应的转换器代码。在另一个实施例中，系统被配置为当它位于预定的数字代码窗口之外时替换对应的转换器代码。

4. 发明授权

US07525381B2 Amplifier structures that enhance transient currents and signal swing 有权
标题翻译：增强瞬态电流和信号摆幅的放大器结构
公开(公告)号：US07525381B2
公开(公告)日：2009-04-28
申请号：US11716169
申请日：2007-03-09
申请人： Franklin M. Murden , Ege Yetis
发明人： Franklin M. Murden , Ege Yetis
IPC分类号： H03F3/45 , H03F1/52
CPC分类号： H03F3/45242 , H03F3/4565 , H03F2203/45682
摘要： Amplifier embodiments are provided that are well suited for systems which require high signal gains and high transient currents that can drive various loads (e.g., capacitive loads). At least one amplifier embodiment is realized with a cascoded complementary differential input stage, a complementary differential output stage, and a bias controller. The output stage includes lower and upper differential pairs of transistors that respectively have lower and upper coupled back gates and the bias controller is configured to provide bias voltages for the lower and upper coupled back gates.
摘要翻译：提供了放大器实施例，其非常适合于需要高信号增益和可以驱动各种负载（例如，电容性负载）的高瞬态电流的系统。使用级联互补差分输入级，互补差分输出级和偏置控制器来实现至少一个放大器实施例。输出级包括分别具有下和上耦合后门的上和下差分对晶体管，并且偏置控制器被配置为提供用于下耦合和上耦合后门的偏置电压。

5. 发明授权

US07382305B1 Reference generators for enhanced signal converter accuracy 有权
标题翻译：用于增强信号转换器精度的参考发生器
公开(公告)号：US07382305B1
公开(公告)日：2008-06-03
申请号：US11711239
申请日：2007-02-26
申请人： Franklin M. Murden , Bac Binh Luu
发明人： Franklin M. Murden , Bac Binh Luu
IPC分类号： H03M1/00
CPC分类号： G05F1/575 , H03M1/145
摘要： Reference generator embodiments are provided with low output impedances to enhance reference stability in the presence of varying loads. The generators are structured to provide these impedances in an efficient manner (i.e., with low supply currents) and also to provide both sink and source currents to better handle large transient current demands. The generators also include cascode structures that facilitate operation with low values of a supply voltage and that provide a low sensitivity to variations in this supply voltage. The embodiments are especially suited for use in signal converter systems.
摘要翻译：参考发生器实施例具有低输出阻抗，以在存在变化的负载的情况下提高参考稳定性。发电机被构造成以有效的方式（即，具有低电源电流）提供这些阻抗，并且还提供吸收和电流电流以更好地处理大的瞬态电流需求。发生器还包括共源共栅结构，便于以较低的电源电压值进行操作，并可为该电源电压的变化提供低灵敏度。这些实施例特别适用于信号转换器系统。

6. 发明授权

US06987471B1 Bias controllers and methods for enhanced system efficiency 有权
标题翻译：偏压控制器和提高系统效率的方法
公开(公告)号：US06987471B1
公开(公告)日：2006-01-17
申请号：US10923636
申请日：2004-08-20
申请人： Franklin M. Murden , James C. Camp
发明人： Franklin M. Murden , James C. Camp
IPC分类号： H03M1/06
CPC分类号： H03M1/127 , H03M1/168
摘要： Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.
摘要翻译：提供偏置控制器，其改变偏置控制信号，使得电子网络的偏置信号（例如，电流信号）快速响应于网络的模拟输入信号的变化率的增加。这增强了包括电子网络的系统的线性。感测变化率的随后的降低，然后以选择为忽略短期变化率变化（例如，调制变化）但是遵循较长期速率 - 速率的速率来选择偏置控制信号的减小，从而提高系统效率，而不牺牲系统线性度。

7. 发明授权

US5861831A Intermediate frequency (IF) sampling clock-to-clock auto-ranging analog-to-digital converter (ADC) and method 失效
标题翻译：中频（IF）采样时钟到时钟自动量程模数转换器（ADC）和方法
公开(公告)号：US5861831A
公开(公告)日：1999-01-19
申请号：US772358
申请日：1996-12-23
申请人： Franklin M. Murden , Carl W. Moreland , Harvey J. Ray , Michael R. Elliott , Marvin J. Young
发明人： Franklin M. Murden , Carl W. Moreland , Harvey J. Ray , Michael R. Elliott , Marvin J. Young
IPC分类号： H03M1/18 , H03M1/62
CPC分类号： H03M1/186
摘要： A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.
摘要翻译：时钟到时钟自动量程ADC直接在IF频带或更高的模拟信号上进行操作，以便在时钟基础上跟踪其增益范围，并产生数字信号，保持模拟信号的高分辨率，无需剪辑或信号灵敏度损失。这通过对具有足够高频率的模拟信号进行采样来实现，峰值检测器可以在至少半个信号周期上精确地确定最大信号电平，然后在下一个采样开始之前复位进入ADC的信号增益期。这确保模拟信号始终在ADC的范围内。根据众所周知的抽样原理，采样模拟信号被混叠到DC与采样频率的一半之间的频率区域。

8. 发明申请

US20130314128A1 CMOS TRANSISTOR LINEARIZATION METHOD 有权
标题翻译： CMOS晶体管线性化方法
公开(公告)号：US20130314128A1
公开(公告)日：2013-11-28
申请号：US13477838
申请日：2012-05-22
申请人： Joseph M. HENSLEY , Franklin M. MURDEN
发明人： Joseph M. HENSLEY , Franklin M. MURDEN
IPC分类号： H03K5/153 , H03K17/687 , G05F3/02
CPC分类号： H03K17/687 , H03M1/06 , H03M1/1245 , H03M1/38
摘要： A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
摘要翻译：用于对模拟输入信号进行采样的电路可以包括设置在衬底上的晶体管和耦合到晶体管的源极和漏极之一的采样电容器。晶体管可以设置在耦合到地的衬底上。晶体管的源极和漏极可以设置在晶体管的背栅极中。模拟输入可以被提供给晶体管的源极和漏极中的一个，并且后栅极可以接收具有低于地的值的背栅极电压。

9. 发明授权

US09246455B2 Three stage amplifier 有权
标题翻译：三级放大器
公开(公告)号：US09246455B2
公开(公告)日：2016-01-26
申请号：US13855175
申请日：2013-04-02
申请人： Franklin M. Murden
发明人： Franklin M. Murden
IPC分类号： H03F3/68 , H03F3/45 , H03G3/00 , H03F3/19
CPC分类号： H03F3/68 , H03F3/19 , H03F3/45179 , H03F3/45183 , H03F2200/408 , H03F2203/45051 , H03F2203/45652 , H03G3/007
摘要： A cascaded amplifier including a pre-amplifier stage having a pair of first transistors, each of the first transistors having a first gate terminal coupled to a first input voltage, a trans-conductive (gm) amplifier stage having a pair of second transistors, each of the second transistors having a second gate terminal coupled to a drain terminal of one of the first transistors, and an integrator amplifier stage having a pair of third transistors, each of the third transistors having a third gate terminal coupled to a drain node of one of the second transistors, each of the third transistors having their drain terminals coupled to an output voltage.
摘要翻译：一种级联放大器，包括具有一对第一晶体管的前置放大器级，每个第一晶体管具有耦合到第一输入电压的第一栅极端子，具有一对第二晶体管的跨导体（gm）放大器级，所述第二晶体管具有耦合到所述第一晶体管之一的漏极端子的第二栅极端子和具有一对第三晶体管的积分器放大器级，所述第三晶体管中的每一个具有耦合到漏极节点的第三栅极端子的第二晶体管，每个第三晶体管的漏极端子耦合到输出电压。

10. 发明申请

US20140266441A1 THREE STAGE AMPLIFIER 有权
标题翻译：三级放大器
公开(公告)号：US20140266441A1
公开(公告)日：2014-09-18
申请号：US13855175
申请日：2013-04-02
申请人： Franklin M. MURDEN
发明人： Franklin M. MURDEN
IPC分类号： H03F3/68 , H03F3/45 , H03G3/00
CPC分类号： H03F3/68 , H03F3/19 , H03F3/45179 , H03F3/45183 , H03F2200/408 , H03F2203/45051 , H03F2203/45652 , H03G3/007
摘要： A cascaded amplifier including a pre-amplifier stage having a pair of first transistors, each of the first transistors having a first gate terminal coupled to a first input voltage, a trans-conductive (gm) amplifier stage having a pair of second transistors, each of the second transistors having a second gate terminal coupled to a drain terminal of one of the first transistors, and an integrator amplifier stage having a pair of third transistors, each of the third transistors having a third gate terminal coupled to a drain node of one of the second transistors, each of the third transistors having their drain terminals coupled to an output voltage.
摘要翻译：一种级联放大器，包括具有一对第一晶体管的前置放大器级，每个第一晶体管具有耦合到第一输入电压的第一栅极端子，具有一对第二晶体管的跨导体（gm）放大器级，所述第二晶体管具有耦合到所述第一晶体管之一的漏极端子的第二栅极端子和具有一对第三晶体管的积分器放大器级，所述第三晶体管中的每一个具有耦合到漏极节点的第三栅极端子的第二晶体管，每个第三晶体管的漏极端子耦合到输出电压。

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