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1. 发明申请

US20070209030A1 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 有权
标题翻译：使用光学规则检查分辨率增强技术的集成电路设备和制造的系统和方法
公开(公告)号：US20070209030A1
公开(公告)日：2007-09-06
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

2. 发明授权

US07080349B1 Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing 有权
标题翻译：开发用于光刻处理的优化光学邻近校正（OPC）碎片脚本的方法
公开(公告)号：US07080349B1
公开(公告)日：2006-07-18
申请号：US10818029
申请日：2004-04-05
申请人： Carl Babcock , Luigi Capodieci
发明人： Carl Babcock , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/68 , G06F2217/12 , Y02P90/265
摘要： A method for developing an optimized layout fragmentation script for an optical proximity correction (OPC) simulation tool. A test pattern layout having at least one structure representing a portion of the integrated circuit layout is provided. Optical proximity correction is iteratively conducted on the test pattern layout for each desired permutation of at least one fragmentation parameter associated with the test pattern layout and, for each permutation, a corrected test pattern layout is generated. A printed simulation of each corrected test pattern layout is made and analyzed to select one of the permutations of the at least one fragmentation parameter to apply to a integrated circuit layout prior to correction with the OPC simulation tool.
摘要翻译：一种用于开发光学邻近校正（OPC）仿真工具的优化布局分片脚本的方法。提供了具有表示集成电路布局的一部分的至少一个结构的测试图案布局。对于与测试图案布局相关联的至少一个碎片参数的每个期望排列，对测试图案布局迭代地进行光学邻近校正，并且对于每个排列，生成校正的测试图案布局。对每个校正的测试图案布局的印刷模拟进行分析，以便在使用OPC模拟工具进行校正之前选择至少一个碎片参数的一个排列以应用于集成电路布局。

3. 发明申请

US20050229125A1 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US20050229125A1
公开(公告)日：2005-10-13
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

4. 发明授权

US07194725B1 System and method for design rule creation and selection 失效
标题翻译：设计规则创建和选择的系统和方法
公开(公告)号：US07194725B1
公开(公告)日：2007-03-20
申请号：US10817132
申请日：2004-04-02
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
摘要翻译：一种产生设计规则的方法，包括生成多个参数变化的几何布局并且模拟每个几何布局如何在晶片上图案化。模拟几何布局中的结构边缘可以基于可制造性进行分类，并且可以创建设计规则以禁止展示不良制造性的布局。

5. 发明授权

US07313769B1 Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
标题翻译：通过考虑布局交互以及额外的可制造性边际来优化集成电路布局
公开(公告)号：US07313769B1
公开(公告)日：2007-12-25
申请号：US10790381
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
摘要翻译：产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

6. 发明授权

US07543256B1 System and method for designing an integrated circuit device 失效
标题翻译：用于设计集成电路器件的系统和方法
公开(公告)号：US07543256B1
公开(公告)日：2009-06-02
申请号：US10790590
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F8/48 , G06F8/447 , G06F17/5022
摘要： A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.
摘要翻译：一种方法包括提供初始的IC器件设计，该设计具有期望的一组电特性。生成对应于初始设备设计的布局表示。仿真工具用于确定布局表示是否对应于具有所需电气特性的IC器件设计。此外，使用仿真工具评估由于工艺变化而设计的IC器件内的结构之间的变化。该变体可用于确定设计是否被优化。

7. 发明授权

US08418105B1 Methods for pattern matching in a double patterning technology-compliant physical design flow 有权
标题翻译：双图案技术兼容物理设计流程中模式匹配的方法
公开(公告)号：US08418105B1
公开(公告)日：2013-04-09
申请号：US13349412
申请日：2012-01-12
申请人： Lynn T. Wang , Vito Dai , Luigi Capodieci
发明人： Lynn T. Wang , Vito Dai , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
摘要翻译：公开了一种用于制造集成电路的方法，其包括根据实施例，为集成电路提供绘制的布局逻辑设计，所述逻辑设计包括多个图案; 检查多种图案以进行双重图案化技术合规; 识别非双重图案化技术兼容图案; 提供用于替换所识别的非双图案化技术兼容图案的双重图案化技术兼容图案，由此创建经修改的逻辑设计; 生成实现修改后的逻辑设计的掩码集; 并且采用该掩模组来实现在半导体衬底中和之上的修改的逻辑设计。

8. 发明授权

US08124300B1 Method of lithographic mask correction using localized transmission adjustment 有权
标题翻译：使用局部传输调整的光刻掩模校正方法
公开(公告)号：US08124300B1
公开(公告)日：2012-02-28
申请号：US10999404
申请日：2004-11-30
申请人： Bhanwar Singh , Luigi Capodieci
发明人： Bhanwar Singh , Luigi Capodieci
IPC分类号： G03F1/00
CPC分类号： G03F1/32 , G03F1/72
摘要： A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.
摘要翻译：公开了一种校正光刻掩模的方法。该方法可以包括检测对应于具有以大于期望尺寸印刷的结构的晶片位置的掩模的位置，并且减小对应于晶片结构的掩模特征的至少一部分的厚度以局部增加透射率的面具功能。

9. 发明申请

US20090144692A1 METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE 审中-公开
标题翻译：用于监测光学近似校正性能的方法和装置
公开(公告)号：US20090144692A1
公开(公告)日：2009-06-04
申请号：US11948151
申请日：2007-11-30
申请人： JASON P. CAIN , Kevin R. Lensing , Bhanwar Singh , Luigi Capodieci , Cyrus E. Tabery
发明人： JASON P. CAIN , Kevin R. Lensing , Bhanwar Singh , Luigi Capodieci , Cyrus E. Tabery
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.
摘要翻译：一种方法包括在晶片上指定多个光学邻近校正度量位置。计量学数据是从至少一个计量站点子集收集的。使用光学邻近校正设计模型为量测站点的子集预测数据值。将收集的测量数据与预测的数据值进行比较以产生光学邻近度校正度量。基于光学邻近度校正度量来识别与光学接近校正设计模型相关联的问题状况。

10. 发明授权

US07269804B2 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US07269804B2
公开(公告)日：2007-09-11
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

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