专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0809294B1 Power semiconductor device structure with vertical PNP transistor 失效
标题翻译：与垂直型PNP晶体管的功率半导体器件结构
公开(公告)号：EP0809294B1
公开(公告)日：2002-01-02
申请号：EP96830293.5
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Scaccianoce, Salvatore , Leonardi, Salvatore
IPC分类号： H01L27/00 , H01L27/082 , H01L21/8224
CPC分类号： H01L27/0821 , H01L21/8224

2. 发明授权

EP0809293B1 Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：与由所述横向晶体管控制的垂直晶体管功率半导体结构
公开(公告)号：EP0809293B1
公开(公告)日：2001-08-29
申请号：EP96830292.7
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Leonardi, Salvatore , Scaccianoce, Salvatore
IPC分类号： H01L27/00 , H01L27/07 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0722

3. 发明授权

EP0639894B1 Circuit for limiting the maximum current supplied to a load by a power transistor 失效
标题翻译：电路的最大电流限制到功率晶体管输送到负载
公开(公告)号：EP0639894B1
公开(公告)日：1997-02-12
申请号：EP93830354.2
申请日：1993-08-18
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Palara, Sergio , Scaccianoce, Salvatore
IPC分类号： H03K17/08 , H03K17/16
CPC分类号： H03K17/08126 , H03K17/0826 , H03K17/16

4. 发明授权

EP0809301B1 An integrated structure with reduced injection of current between homologous regions 失效
标题翻译：一体化结构与同源区之间减少注入电流
公开(公告)号：EP0809301B1
公开(公告)日：2000-06-28
申请号：EP96830277.8
申请日：1996-05-14
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Scaccianoce, Salvatore , Sueri, Stefano
IPC分类号： H01L29/00 , H01L27/082
CPC分类号： H01L27/0828 , H01L27/0821

5. 发明公开

EP0810503A1 An integrated circuit with a device having a predetermined reverse conduction threshold and a thermal compensation device with Vbe multipliers 失效
标题翻译：一种集成电路与装置具有由Vbe的乘法器装置上的一定反向电压阈值和温度补偿装置
公开(公告)号：EP0810503A1
公开(公告)日：1997-12-03
申请号：EP96830276.0
申请日：1996-05-14
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Scaccianoce, Salvatore
IPC分类号： G05F1/00 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0211 , H01L27/0652
摘要： A monolithic, integrated semiconductor circuit comprising a high-voltage device (210) with a predetermined reverse-conduction threshold, typically a chain of Zener diodes (220-240) has, connected in series therewith, a thermal compensation device (250) constituted by a plurality of Vbe multipliers connected in series with one another. Each of the Vbe multipliers is formed by a resistive divider (R1i, R2i) and a low-voltage transistor (Ti) or two or more low-voltage transistors in a Darlington configuration.
摘要翻译：一种单片集成半导体电路包括高电压设备（210）与预定的反向导通的阈值，典型地，齐纳二极管的链（220-240）已经串联连接有与，由构成热补偿装置（250）串联连接彼此的Vbe乘法器的复数。 Vbe的乘法器中的每一个由一个电阻分压器（R 1I，R 2I）和一个低电压晶体管（Ti）的或两种或更多种低电压晶体管在达林顿结构形成。

6. 发明公开

EP0809301A1 An integrated structure with reduced injection of current between homologous regions 失效
标题翻译： Integrierte Struktur mit reduziertem Injektionsstrom zwischen homologen Gebieten
公开(公告)号：EP0809301A1
公开(公告)日：1997-11-26
申请号：EP96830277.8
申请日：1996-05-14
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Scaccianoce, Salvatore , Sueri, Stefano
IPC分类号： H01L29/00 , H01L27/082
CPC分类号： H01L27/0828 , H01L27/0821
摘要： An integrated semiconductor structure (500) comprises two homologous P-type regions (120 and 130) formed within an N-type epitaxial layer (110). A P-type region (510) formed in the portion of the epitaxial layer (110) disposed between the two P-type regions (120 and 130) includes within it an N-type region (520); this N region (520) is electrically connected to the P region (130) by means of a surface metal contact (530). The structure reduces the injection of current between the P region 120 and the P region 130, at the same time preventing any vertical parasitic transistors from being switched on.
摘要翻译：集成半导体结构（500）包括形成在N型外延层（110）内的两个同源P型区域（120和130）。形成在设置在两个P型区域（120和130）之间的外延层（110）的部分中的P型区域（510）在其内包括N型区域（520）; 该N区域（520）通过表面金属触点（530）电连接到P区域（130）。该结构减少了P区域120和P区域130之间的电流注入，同时防止任何垂直寄生晶体管导通。

7. 发明公开

EP0809293A1 Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：线性电容器
公开(公告)号：EP0809293A1
公开(公告)日：1997-11-26
申请号：EP96830292.7
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Leonardi, Salvatore , Scaccianoce, Salvatore
IPC分类号： H01L27/00 , H01L27/07 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0722
摘要： A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.
摘要翻译：一种功率半导体结构（200），特别是在VIPower技术中，由N型半导体材料（110）的芯片制成，包括具有集电极或漏极的双极或场效应垂直功率晶体管（125,120,110）这种N型材料（110）中的区域; 半导体结构包括PNP双极侧向功率晶体管（210,110,220），其具有基本上与垂直功率晶体管的集电极或漏极区共同的N型材料（110）中的基极区域。

8. 发明公开

EP0809294A1 Power semiconductor device structure with vertical PNP transistor 失效
标题翻译： Leistungshalbleiterbauelementstruktur mit vertikalem PNP晶体管
公开(公告)号：EP0809294A1
公开(公告)日：1997-11-26
申请号：EP96830293.5
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Scaccianoce, Salvatore , Leonardi, Salvatore
IPC分类号： H01L27/00 , H01L27/082 , H01L21/8224
CPC分类号： H01L27/0821 , H01L21/8224
摘要： Power semiconductor device structure formed in a chip (100) of semiconductor material consisting of an N-type substrate (103) and an N-type epitaxial layer (118). The structure comprises a P-type insulation region (106, 121) which forms a pocket (124) in which a control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region (109, 127) consisting of an buried region (109) between the substrate (103) and the epitaxial layer (118) and a contact region (127); the P region (109, 127) delimits a base N region (130) within which an emitter P region (148) is formed.
摘要翻译：功率半导体器件结构形成在由N型衬底（103）和N型外延层（118）组成的半导体材料的芯片（100）中。该结构包括形成其中形成控制电路的口袋（124）和多个完全绝缘的PNP功率晶体管的P型绝缘区域（106,121）。每个PNP功率晶体管包括由衬底（103）和外延层（118）之间的掩埋区（109）和接触区（127）组成的P型集电极区（109,127）。 P区域（109,127）限定形成发射极P区域（148）的基极N区域（130）。

9. 发明授权

EP0810503B1 An integrated circuit with a device having a predetermined reverse conduction threshold and a thermal compensation device with Vbe multipliers 失效
标题翻译：一种集成电路与装置具有由Vbe的乘法器装置上的一定反向电压阈值和温度补偿装置
公开(公告)号：EP0810503B1
公开(公告)日：2001-12-19
申请号：EP96830276.0
申请日：1996-05-14
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Scaccianoce, Salvatore
IPC分类号： G05F1/00 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0211 , H01L27/0652

10. 发明公开

EP0639894A1 Circuit for limiting the maximum current supplied to a load by a power transistor 失效
标题翻译： Schaltung zur Begrenzung des Maximalstroms，den ein Leistungstransistor an eine Last liefert。
公开(公告)号：EP0639894A1
公开(公告)日：1995-02-22
申请号：EP93830354.2
申请日：1993-08-18
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Palara, Sergio , Scaccianoce, Salvatore
IPC分类号： H03K17/08 , H03K17/16
CPC分类号： H03K17/08126 , H03K17/0826 , H03K17/16
摘要： A limiter circuit for the maximum current passed from a power transistor (T'p) to a load (ZL) connected to an output terminal of the transistor, being of a type which comprises an error amplifier (1'), a driver circuit (P') for said transistor (T'p), and a means of detecting the current (IL) flowing through said load (ZL) provided with at least first and second terminals, is characterized in that it comprises a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal of the amplifier (1'), one input (B') of said amplifier (1') being connected to said first terminal of (Rs)and the other input (A') connected to said second terminal of (Rs). The introduction of said circuit block lowers the open-ring system gain making it stable and producing a smooth reduction of any rise in the load current (IL).
摘要翻译：用于从功率晶体管（T'p）到连接到晶体管的输出端子的负载（ZL）的最大电流的限幅器电路，其包括误差放大器（1'），驱动器电路 P'），以及检测流过设置有至少第一和第二端子的所述负载（ZL）的电流（IL）的装置，其特征在于，其包括电路块（2）具有连接到（T'p）的控制端的输入端和连接到放大器（1'）的电流发生器内部的输出端，所述放大器（1'）的一个输入（B'）连接到所述（Rs）的第一端子和连接到（Rs）的所述第二端子的另一输入端（A'）。所述电路块的引入降低了开环系统增益，使其稳定，并且可以平滑地减少负载电流（IL）的任何上升。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式