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1. 发明授权

EP0809294B1 Power semiconductor device structure with vertical PNP transistor 失效
标题翻译：与垂直型PNP晶体管的功率半导体器件结构
公开(公告)号：EP0809294B1
公开(公告)日：2002-01-02
申请号：EP96830293.5
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Scaccianoce, Salvatore , Leonardi, Salvatore
IPC分类号： H01L27/00 , H01L27/082 , H01L21/8224
CPC分类号： H01L27/0821 , H01L21/8224

2. 发明授权

EP0809293B1 Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：与由所述横向晶体管控制的垂直晶体管功率半导体结构
公开(公告)号：EP0809293B1
公开(公告)日：2001-08-29
申请号：EP96830292.7
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Leonardi, Salvatore , Scaccianoce, Salvatore
IPC分类号： H01L27/00 , H01L27/07 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0722

3. 发明授权

EP0639894B1 Circuit for limiting the maximum current supplied to a load by a power transistor 失效
标题翻译：电路的最大电流限制到功率晶体管输送到负载
公开(公告)号：EP0639894B1
公开(公告)日：1997-02-12
申请号：EP93830354.2
申请日：1993-08-18
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Palara, Sergio , Scaccianoce, Salvatore
IPC分类号： H03K17/08 , H03K17/16
CPC分类号： H03K17/08126 , H03K17/0826 , H03K17/16

4. 发明公开

EP0809293A1 Power semiconductor structure with lateral transistor driven by vertical transistor 失效
标题翻译：线性电容器
公开(公告)号：EP0809293A1
公开(公告)日：1997-11-26
申请号：EP96830292.7
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Leonardi, Salvatore , Scaccianoce, Salvatore
IPC分类号： H01L27/00 , H01L27/07 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0722
摘要： A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.
摘要翻译：一种功率半导体结构（200），特别是在VIPower技术中，由N型半导体材料（110）的芯片制成，包括具有集电极或漏极的双极或场效应垂直功率晶体管（125,120,110）这种N型材料（110）中的区域; 半导体结构包括PNP双极侧向功率晶体管（210,110,220），其具有基本上与垂直功率晶体管的集电极或漏极区共同的N型材料（110）中的基极区域。

5. 发明公开

EP0782197A1 Integrated electronic device with reduced parasitic currents, and corresponding method 失效
标题翻译：集成电子元件具有降低的寄生电流及其方法
公开(公告)号：EP0782197A1
公开(公告)日：1997-07-02
申请号：EP95830558.3
申请日：1995-12-29
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Graziano, Vito
IPC分类号： H01L29/00 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0203
摘要： The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.
摘要翻译：本发明涉及一种在在包括基板（1），具有第一导电类型，其中形成半导体材料单片集成电子装置中的第一（2）和第二扩散区（3）的第二导电类型与所述基板（ 1）和所述第一（2）和第二（3）的扩散区域分别包括一个基区，集电区和发射极的晶体管的区域（TP1）和其特征在于在所述第二扩散区做了（3）上形成第三扩散区（8）所述第一类型的所述第二扩散区，以提供具有导电性的（3）串联放置与所述晶体管（TP1）的发射极区，而带负backfeeding它并把它与至饱和一阻抗路径（R）所得的减小其电流的电流由于其上的最大的增益和限制。

6. 发明授权

EP0782197B1 Integrated electronic device with reduced parasitic currents, and corresponding method 失效
标题翻译：集成电子元件具有降低的寄生电流及其方法
公开(公告)号：EP0782197B1
公开(公告)日：2001-06-06
申请号：EP95830558.3
申请日：1995-12-29
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Graziano, Vito
IPC分类号： H01L29/00 , H01L27/082
CPC分类号： H01L27/0821 , H01L27/0203

7. 发明公开

EP0810662A1 An integrated device in an "emitter switching" configuration and with a cellular structure 失效
标题翻译： Integriertes Bauteil在Emitterschalteranordnung und mit einer zellularen Struktur
公开(公告)号：EP0810662A1
公开(公告)日：1997-12-03
申请号：EP96830306.5
申请日：1996-05-29
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Graziano, Vito , La Barbera, Atanasio , Sueri, Stefano
IPC分类号： H01L27/00 , H01L27/082 , H01L29/423 , H01L23/482
CPC分类号： H01L27/0825
摘要： An integrated device comprises a high-voltage transistor and a low-voltage transistor in an emitter-switching configuration integrated in a chip (400) of semiconductor material comprising a buried P-type region (120) and a corresponding P-type contact region (405) which delimit a portion of semiconductor material within which the low-voltage transistor is formed. The contact region (405) has a network structure such as to divide this portion of semiconductor material into a plurality of cells (410) within each of which there is an elemental P-type base region (425) and an elemental N-type emitter region (430) of the low-voltage transistor. The elemental regions (425) and (430) of the various cells (410) are electrically connected to one another by means of surface metal contacts.
摘要翻译：集成器件包括集成在半导体材料的芯片（400）中的发射极切换配置中的高压晶体管和低压晶体管，该芯片（400）包括掩埋P型区域（120）和相应的P型接触区域 405），其限定了形成低压晶体管的半导体材料的一部分。接触区域（405）具有将半导体材料的该部分分成多个单元（410）的网络结构，其中每个单元具有元素P型基极区域（425）和元素N型发射极低压晶体管的区域（430）。各种电池（410）的元件区域（425）和（430）通过表面金属触点彼此电连接。

8. 发明公开

EP0740491A1 Bipolar power device having an integrated thermal protection for driving electric loads 失效
标题翻译：双极开关，具有集成的热保护电路，用于控制电负载
公开(公告)号：EP0740491A1
公开(公告)日：1996-10-30
申请号：EP95830167.3
申请日：1995-04-28
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO , SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Aiello, Natale , La Barbera, Atanasio , Palara, Sergio
IPC分类号： H05B41/00 , H02H5/04 , H03K17/08 , H05B41/29
CPC分类号： H05B41/2856 , H02H5/044 , H03K17/08126 , H03K2017/0806
摘要： A monolithically integrated power device for driving electrical loads comprises a power stage (1) including a high-voltage bipolar transistor (TR1) and a low-voltage auxiliary transistor (M or TR2) cascade-connected and inserted between a first power supply terminal (C) and a second power supply terminal (S) of the device. The power device also comprises a driver circuit (4) for the power stage (1) having an input connected to an input terminal (IN) of the device.
In accordance with the present invention the device includes a circuit (3) for protection thereof against an excessive temperature rise and controlling power down of the power stage (1). It comprises specifically a temperature sensing circuit (5) which generates a signal dependent on the temperature present in the device, a comparator circuit (6) which receives this signal and compares it with a reference voltage (VREF) and at least a first switch circuit (I1) generating an interdiction signal when the temperature in the device exceeds a preset maximum value and which is interlocked with an output of the comparator circuit and connected functionally through its output to the power stage.
The device is advantageously usable e.g. in a fluorescent lamp driving circuit, that is to say the so-called "lamp ballast".
摘要翻译：用于驱动电气负载单片集成功率器件包括一个高压双极型晶体管（TR1）和低压辅助晶体管（M或TR2）一个功率级（1）级联连接和第一电源端之间插入（ C）和所述装置的第二电源端子（S）。功率器件，以便包括用于具有到连接到该装置的输入端（IN）上的输入功率级（1）的驱动电路（4）。在与本发明雅舞蹈的装置包括用于保护其对抗在过度的温度上升，并控制功率的功率级（1）的向下的电路（3）。它专门包括一个温度检测电路（5），该基因率的信号依赖于存在于所述装置中的温度，一个比较器电路（6），其接收该信号并将它与一个参考电压（VREF）和至少一个第一开关电路比较（I1）在遮断信号产生时该装置中的温度超过预设最大值和所有其互锁在比较器电路的输出，并通过其输出到功率级功能性地连接。该装置有利地是可使用的E.G. 在荧光灯驱动电路，确实就是所谓的“灯镇流器”。

9. 发明公开

EP0639894A1 Circuit for limiting the maximum current supplied to a load by a power transistor 失效
标题翻译： Schaltung zur Begrenzung des Maximalstroms，den ein Leistungstransistor an eine Last liefert。
公开(公告)号：EP0639894A1
公开(公告)日：1995-02-22
申请号：EP93830354.2
申请日：1993-08-18
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Palara, Sergio , Scaccianoce, Salvatore
IPC分类号： H03K17/08 , H03K17/16
CPC分类号： H03K17/08126 , H03K17/0826 , H03K17/16
摘要： A limiter circuit for the maximum current passed from a power transistor (T'p) to a load (ZL) connected to an output terminal of the transistor, being of a type which comprises an error amplifier (1'), a driver circuit (P') for said transistor (T'p), and a means of detecting the current (IL) flowing through said load (ZL) provided with at least first and second terminals, is characterized in that it comprises a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal of the amplifier (1'), one input (B') of said amplifier (1') being connected to said first terminal of (Rs)and the other input (A') connected to said second terminal of (Rs). The introduction of said circuit block lowers the open-ring system gain making it stable and producing a smooth reduction of any rise in the load current (IL).
摘要翻译：用于从功率晶体管（T'p）到连接到晶体管的输出端子的负载（ZL）的最大电流的限幅器电路，其包括误差放大器（1'），驱动器电路 P'），以及检测流过设置有至少第一和第二端子的所述负载（ZL）的电流（IL）的装置，其特征在于，其包括电路块（2）具有连接到（T'p）的控制端的输入端和连接到放大器（1'）的电流发生器内部的输出端，所述放大器（1'）的一个输入（B'）连接到所述（Rs）的第一端子和连接到（Rs）的所述第二端子的另一输入端（A'）。所述电路块的引入降低了开环系统增益，使其稳定，并且可以平滑地减少负载电流（IL）的任何上升。

10. 发明公开

EP0809294A1 Power semiconductor device structure with vertical PNP transistor 失效
标题翻译： Leistungshalbleiterbauelementstruktur mit vertikalem PNP晶体管
公开(公告)号：EP0809294A1
公开(公告)日：1997-11-26
申请号：EP96830293.5
申请日：1996-05-21
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Aiello, Natale , Patti, Davide , Scaccianoce, Salvatore , Leonardi, Salvatore
IPC分类号： H01L27/00 , H01L27/082 , H01L21/8224
CPC分类号： H01L27/0821 , H01L21/8224
摘要： Power semiconductor device structure formed in a chip (100) of semiconductor material consisting of an N-type substrate (103) and an N-type epitaxial layer (118). The structure comprises a P-type insulation region (106, 121) which forms a pocket (124) in which a control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region (109, 127) consisting of an buried region (109) between the substrate (103) and the epitaxial layer (118) and a contact region (127); the P region (109, 127) delimits a base N region (130) within which an emitter P region (148) is formed.
摘要翻译：功率半导体器件结构形成在由N型衬底（103）和N型外延层（118）组成的半导体材料的芯片（100）中。该结构包括形成其中形成控制电路的口袋（124）和多个完全绝缘的PNP功率晶体管的P型绝缘区域（106,121）。每个PNP功率晶体管包括由衬底（103）和外延层（118）之间的掩埋区（109）和接触区（127）组成的P型集电极区（109,127）。 P区域（109,127）限定形成发射极P区域（148）的基极N区域（130）。

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