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1. 发明申请

WO2003077630A2 METHOD AND APPARATUS FOR SYNTHESIS 审中-公开
标题翻译：合成方法和装置
公开(公告)号：WO2003077630A2
公开(公告)日：2003-09-25
申请号：PCT/US2003/002984
申请日：2003-01-31
申请人： CADENCE DESIGN SYSTEMS, INC. , TEIG, Steven , ASMUS, Hetzel
发明人： TEIG, Steven , ASMUS, Hetzel
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F17/5045 , Y10S707/99931 , Y10S707/99943
摘要： Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure base don the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (49 replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.
摘要翻译：本发明的一些实施例提供了一种预制子网络的方法。该方法（1）生成执行功能的子网络，（2）基于该功能生成参数，（3）将子网络存储在生成的参数的存储结构基础中。在一些实施例中，所生成的子网具有多个电路元件。此外，在一些实施例中，所生成的子网络执行一组两个或更多个功能。一些实施例以编码的方式存储每个生成的子网络。一些实施例提供了一种用于产生设计的电路描述的方法。该方法（1）从设计中选择候选子网络，（2）识别由子网执行的输出功能，（3）基于所识别的输出功能，从存储结构中识别替换子网络，存储替换子网络，（49）在特定条件下用所标识的替换子网络替换所选择的候选子网络。在一些实施例中，执行该方法将设计映射到特定技术库，一些实施例提供数据存储结构，其基于从所述子网的输出功能导出的参数来存储多个子网。

2. 发明申请

WO2003077630A3 METHOD AND APPARATUS FOR SYNTHESIS 审中-公开
公开(公告)号：WO2003077630A3
公开(公告)日：2003-09-25
申请号：PCT/US2003/002984
申请日：2003-01-31
申请人： CADENCE DESIGN SYSTEMS, INC. , TEIG, Steven , ASMUS, Hetzel
发明人： TEIG, Steven , ASMUS, Hetzel
IPC分类号： G06F17/50
摘要： A method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function (605), (2) generates a parameter based on this function (610), and (3) stores the sub-network in a storage structure based on the generated parameters (635).

3. 发明申请

WO2004051403A2 METHOD, APPARATUS, AND SYSTEM FOR ROUTING 审中-公开
标题翻译：方法，装置和路由系统
公开(公告)号：WO2004051403A2
公开(公告)日：2004-06-17
申请号：PCT/US2003/036873
申请日：2003-11-18
申请人： CADENCE DESIGN SYSTEMS, INC. , FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
发明人： FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
IPC分类号： G06F
CPC分类号： G06F1/00 , G06F17/50
摘要： Some embodiments of the invention provide a method of identifying global routes for nets in a region of a layout with multiple layers. In the region, each net has a set of routable elements. The method partitions each layer of the region into several sub-regions. For each net, the method then identifies a route that connects the sub-regions that contain the net’s set of routable elements, where some routes have at least one non-Manhattan edge and traverse sub-regions on multiple layers. Some embodiments search for a three-dimensional global path between first and second sets of routable elements in a region of a layout that has multiple layers. These embodiments partition the region into several sub-regions. They then perform a path search to identify a path between a first set of sub-regions that contains the first-set elements and a second set of sub-regions that contain a second-set element. During the path search, these embodiments explore expansions along Manhattan and non-Manhattan routing directions between the sub-regions on a plurality of layers. Some embodiments define a routing graph that has several of nodes on several layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. These embodiments then use the routing graph to identify routes.
摘要翻译：本发明的一些实施例提供了一种识别具有多个层的布局的区域中的网络的全局路由的方法。在该区域，每个网络具有一组可路由元素。该方法将该区域的每个层分成几个子区域。对于每个网络，该方法然后识别连接包含网络可路由元件集合的子区域的路由，其中一些路由具有至少一个非曼哈顿边缘并遍历多个层上的子区域。一些实施例在具有多个层的布局的区域中搜索第一和第二组可路由元件之间的三维全局路径。这些实施例将该区域划分成几个子区域。然后，他们执行路径搜索以识别包含第一集合元素的第一组子区域和包含第二集合元素的第二组子区域之间的路径。在路径搜索期间，这些实施例探索沿着曼哈顿的扩展和在多个层之间的子区域之间的非曼哈顿路由方向。一些实施例定义了在几个层上具有几个节点的路由图，其中每个节点表示层上的子区域。在图中，每层上的节点之间有一组边。在一层上，至少有一组边缘既不正交也不平行于另一层上的一组边缘。然后，这些实施例使用路由图来识别路由。

4. 发明公开

EP1470506A2 METHOD AND APPARATUS FOR SYNTHESIS 审中-公开
标题翻译：方法和设备合成
公开(公告)号：EP1470506A2
公开(公告)日：2004-10-27
申请号：EP03744591.3
申请日：2003-01-31
申请人： Cadence Design Systems, Inc.
发明人： TEIG, Steven , ASMUS, Hetzel
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , Y10S707/99931 , Y10S707/99943
摘要： A method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function (605), (2) generates a parameter based on this function (610), and (3) stores the sub-network in a storage structure based on the generated parameters (635).

5. 发明公开

EP1759321A2 METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS 审中-公开
标题翻译：方法和装置设计LAYOUTS集成电路的
公开(公告)号：EP1759321A2
公开(公告)日：2007-03-07
申请号：EP05740549.0
申请日：2005-04-29
申请人： Cadence Design Systems, Inc.
发明人： SCHEFFER, Louis, K. , TEIG, Steven
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including (2205) receiving the upper layout containing features and modifications to features, (2215) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, (2220) selecting a feature in the upper layout, (2225) retrieving, from the density map, the geometry coverage of a sub-region below the feature, (2230) determining a vertical deviation of the feature using the geometry coverage, (2235) determining an alteration to the modification using the vertical deviation, (2240) applying the alteration to the modification and (2245) repeating for all features.

6. 发明公开

EP1759322A2 METHOS AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS 审中-公开
标题翻译：方法和装置设计LAYOUTS集成电路的
公开(公告)号：EP1759322A2
公开(公告)日：2007-03-07
申请号：EP05740554.0
申请日：2005-04-29
申请人： Cadence Design Systems, Inc.
发明人： SCHEFFER, Louis, K. , TEIG, Steven
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that is calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or data describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, an upper layout for an upper of an IC are modified using information (such a density map) relating to a lower layout for a lower layer of the IC.

7. 发明申请

WO2011162858A1 RESCALING 审中-公开
标题翻译：重新缩放
公开(公告)号：WO2011162858A1
公开(公告)日：2011-12-29
申请号：PCT/US2011/031482
申请日：2011-04-06
申请人： TABULA, INC. , WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
发明人： WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
IPC分类号： H03K19/173
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/505 , G06F17/5054
摘要： A novel method for designing an integrated circuit ("IC") by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
摘要翻译：公开了一种通过在IC的设计中重新调整原始电路组来设计集成电路（“IC”）的新颖方法。要重新缩放的原始电路组包括顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联。该方法产生包括电路的多个复制集合的重新定标的电路集合。每个电路副本集合包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。该方法将每个电路副本中的节点连接到另一副本集中的逻辑等效节点。该方法用重新定标的电路组替换原始电路组。

8. 发明申请

WO2011123151A1 SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE 审中-公开
标题翻译：减少重新配置电力使用的系统和方法
公开(公告)号：WO2011123151A1
公开(公告)日：2011-10-06
申请号：PCT/US2010/053487
申请日：2010-10-21
申请人： TABULA INC. , HUANG, Randy, R. , VOOGEL, Martin , HU, Jingcao , TEIG, Steven
发明人： HUANG, Randy, R. , VOOGEL, Martin , HU, Jingcao , TEIG, Steven
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , G06F17/50 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H03K19/1737 , H03K19/17748 , H03K19/17756 , H03K19/17784 , H03K19/17796
摘要： A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.
摘要翻译：一种用于降低可重构集成电路中的功耗的系统和方法。一些实施例提供了减少要重新配置的比特数的布局和路由程序。一些实施例提供了放置和路由程序，其增加了在某些时间不需要重新配置的电路组的数量。一些实施例包括选择性地阻止重新配置的电路。

9. 发明申请

WO2009002600A1 RESTRUCTURING DATA FROM A TRACE BUFFER OF A CONFIGURABLE IC 审中-公开
标题翻译：从可配置IC的跟踪缓冲区重新构建数据
公开(公告)号：WO2009002600A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/061072
申请日：2008-04-21
申请人： TABULA, INC. , HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
发明人： HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17764
摘要： Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the trace buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.
摘要翻译：一些实施例提供了一种从可配置IC输出来自跟踪缓冲器的第一组数据位的方法。第一组数据位的每个位在可配置电路中同时生成，并且在一些实施例中，第一组数据位的多个数据位不会同时到达跟踪缓冲器。该方法还确定第一组数据比特的一组相对延迟，并通过补偿相对延迟将第一组数据比特排列成第二组数据比特。

10. 发明申请

WO2008115243A2 CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS 审中-公开
标题翻译：具有存储元件的布线布的可配置IC
公开(公告)号：WO2008115243A2
公开(公告)日：2008-09-25
申请号：PCT/US2007/069831
申请日：2007-05-27
申请人： TABULA, INC. , TEIG, Steven , SCHMIT, Herman , REDGRAVE, Jason , HUANG, Randy, Renfu
发明人： TEIG, Steven , SCHMIT, Herman , REDGRAVE, Jason , HUANG, Randy, Renfu
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17736
摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
摘要翻译：一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或来自这种组件的先前信号是否存储在路由结构内。源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

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