专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004051403A2 METHOD, APPARATUS, AND SYSTEM FOR ROUTING 审中-公开
标题翻译：方法，装置和路由系统
公开(公告)号：WO2004051403A2
公开(公告)日：2004-06-17
申请号：PCT/US2003/036873
申请日：2003-11-18
申请人： CADENCE DESIGN SYSTEMS, INC. , FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
发明人： FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
IPC分类号： G06F
CPC分类号： G06F1/00 , G06F17/50
摘要： Some embodiments of the invention provide a method of identifying global routes for nets in a region of a layout with multiple layers. In the region, each net has a set of routable elements. The method partitions each layer of the region into several sub-regions. For each net, the method then identifies a route that connects the sub-regions that contain the net’s set of routable elements, where some routes have at least one non-Manhattan edge and traverse sub-regions on multiple layers. Some embodiments search for a three-dimensional global path between first and second sets of routable elements in a region of a layout that has multiple layers. These embodiments partition the region into several sub-regions. They then perform a path search to identify a path between a first set of sub-regions that contains the first-set elements and a second set of sub-regions that contain a second-set element. During the path search, these embodiments explore expansions along Manhattan and non-Manhattan routing directions between the sub-regions on a plurality of layers. Some embodiments define a routing graph that has several of nodes on several layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. These embodiments then use the routing graph to identify routes.
摘要翻译：本发明的一些实施例提供了一种识别具有多个层的布局的区域中的网络的全局路由的方法。在该区域，每个网络具有一组可路由元素。该方法将该区域的每个层分成几个子区域。对于每个网络，该方法然后识别连接包含网络可路由元件集合的子区域的路由，其中一些路由具有至少一个非曼哈顿边缘并遍历多个层上的子区域。一些实施例在具有多个层的布局的区域中搜索第一和第二组可路由元件之间的三维全局路径。这些实施例将该区域划分成几个子区域。然后，他们执行路径搜索以识别包含第一集合元素的第一组子区域和包含第二集合元素的第二组子区域之间的路径。在路径搜索期间，这些实施例探索沿着曼哈顿的扩展和在多个层之间的子区域之间的非曼哈顿路由方向。一些实施例定义了在几个层上具有几个节点的路由图，其中每个节点表示层上的子区域。在图中，每层上的节点之间有一组边。在一层上，至少有一组边缘既不正交也不平行于另一层上的一组边缘。然后，这些实施例使用路由图来识别路由。

2. 发明申请

WO2002046975A3 ROUTING METHOD AND APPARATUS 审中-公开
公开(公告)号：WO2002046975A3
公开(公告)日：2002-06-13
申请号：PCT/US2001/047016
申请日：2001-12-06
申请人： SIMPLEX SOLUTIONS, INC. , TEIG, Steven , BUSET, Oscar , CALDWELL, Andrew , JACQUES, Etienne , FRANKLE, Jonathan, A. , CHAO, Heng-Yi
发明人： TEIG, Steven , BUSET, Oscar , CALDWELL, Andrew , JACQUES, Etienne , FRANKLE, Jonathan, A. , CHAO, Heng-Yi
IPC分类号： G06F17/50
摘要： The invention is directed towards routing method and apparatus. Some embodiments provide a routing that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

3. 发明申请

WO2011162858A1 RESCALING 审中-公开
标题翻译：重新缩放
公开(公告)号：WO2011162858A1
公开(公告)日：2011-12-29
申请号：PCT/US2011/031482
申请日：2011-04-06
申请人： TABULA, INC. , WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
发明人： WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
IPC分类号： H03K19/173
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/505 , G06F17/5054
摘要： A novel method for designing an integrated circuit ("IC") by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
摘要翻译：公开了一种通过在IC的设计中重新调整原始电路组来设计集成电路（“IC”）的新颖方法。要重新缩放的原始电路组包括顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联。该方法产生包括电路的多个复制集合的重新定标的电路集合。每个电路副本集合包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。该方法将每个电路副本中的节点连接到另一副本集中的逻辑等效节点。该方法用重新定标的电路组替换原始电路组。

4. 发明申请

WO2009151934A1 DECISION MODULES 审中-公开
标题翻译：决策模块
公开(公告)号：WO2009151934A1
公开(公告)日：2009-12-17
申请号：PCT/US2009/045096
申请日：2009-05-22
申请人： TABULA, INC. , CALDWELL, Andrew , TEIG, Steven
发明人： CALDWELL, Andrew , TEIG, Steven
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081
摘要： An abstract decision module primitive for placement within a logical representation ( i.e ., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.
摘要翻译：描述了用于放置在电路设计的逻辑表示（即，网表中）的抽象决策模块原语。决策模块原语接收网表的给定功能或段的输入替代解决方案。替代解决方案包括功能等同，但在网表的功能或段的结构上不同的实现。所述决策模块基元可选择在连接到所述网表之一的输入之间，以基于约束信息为所述网表提供完整的功能定义。当在设计过程的各个阶段确定附加约束信息时，可以更新决策模块的所选择的输入。此外，当识别出额外的约束信息时，可以向决策模块的输入添加和/或从其中删除网表的给定功能或段的替代解决方案。

5. 发明申请

WO2009002600A1 RESTRUCTURING DATA FROM A TRACE BUFFER OF A CONFIGURABLE IC 审中-公开
标题翻译：从可配置IC的跟踪缓冲区重新构建数据
公开(公告)号：WO2009002600A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/061072
申请日：2008-04-21
申请人： TABULA, INC. , HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
发明人： HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17764
摘要： Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the trace buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.
摘要翻译：一些实施例提供了一种从可配置IC输出来自跟踪缓冲器的第一组数据位的方法。第一组数据位的每个位在可配置电路中同时生成，并且在一些实施例中，第一组数据位的多个数据位不会同时到达跟踪缓冲器。该方法还确定第一组数据比特的一组相对延迟，并通过补偿相对延迟将第一组数据比特排列成第二组数据比特。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式