专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060284245A1 SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有弯曲表面的SONOS存储器件及其制造方法
公开(公告)号：US20060284245A1
公开(公告)日：2006-12-21
申请号：US11424524
申请日：2006-06-15
申请人： Byung-Gook Park , Jung-Hoon Lee
发明人： Byung-Gook Park , Jung-Hoon Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/1033 , H01L29/4232 , H01L29/66833 , H01L29/7854
摘要： A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an improvement in erasing speed.
摘要翻译：提供了一种新的SONOS存储器件，其中多个电介质层（ONO层）的常规平面表面替代地形成有诸如圆柱形的弯曲表面，并且包括其制造方法。阻挡氧化物的上表面的曲率半径可以被设计为大于隧道氧化物的下表面的曲率半径，其阻止电子在擦除时通过反向隧道穿过阻塞氧化物。结果，SONOS存储器件显示出擦除速度的改进。

2. 发明授权

US07560764B2 SONOS memory device having curved surface and method for fabricating the same 有权
标题翻译：具有曲面的SONOS记忆装置及其制造方法
公开(公告)号：US07560764B2
公开(公告)日：2009-07-14
申请号：US11424524
申请日：2006-06-15
申请人： Byung-Gook Park , Jung-Hoon Lee
发明人： Byung-Gook Park , Jung-Hoon Lee
IPC分类号： H01L23/62
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/1033 , H01L29/4232 , H01L29/66833 , H01L29/7854
摘要： A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same.A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an improvement in erasing speed.
摘要翻译：提供了一种新的SONOS存储器件，其中多个电介质层（ONO层）的常规平面表面替代地形成有诸如圆柱形的弯曲表面，并且包括其制造方法。阻挡氧化物的上表面的曲率半径可以被设计为大于隧道氧化物的下表面的曲率半径，其阻止电子在擦除时通过反向隧道穿过阻塞氧化物。结果，SONOS存储器件显示出擦除速度的改进。

3. 发明授权

US09111843B2 LED display apparatus having active devices and fabrication method thereof 有权
标题翻译：具有有源器件的LED显示装置及其制造方法
公开(公告)号：US09111843B2
公开(公告)日：2015-08-18
申请号：US13095295
申请日：2011-04-27
申请人： Byung-Gook Park , Chang Su Seo , Byung Doo Yoo , Keun Kee Hong , Sang Yeop Jee , Jae Min Jeong
发明人： Byung-Gook Park , Chang Su Seo , Byung Doo Yoo , Keun Kee Hong , Sang Yeop Jee , Jae Min Jeong
IPC分类号： H01L25/16 , H01L23/00 , H01L27/12 , H01L33/20 , H01L33/40
CPC分类号： H01L25/167 , H01L24/95 , H01L27/1214 , H01L27/1255 , H01L33/20 , H01L33/40 , H01L2224/95085 , H01L2924/01322 , H01L2924/12036 , H01L2924/12041 , H01L2924/12044 , H01L2924/00
摘要： An active matrix LED display apparatus and a fabrication method thereof are provided. The active matrix LED display apparatus enables to miniaturize pixel by a formation of wiring on bottom layer and an assembly of each block through each eutectic layer into each transistor block receptor and/or each LED block receptor formed according to each color element unit, and to be embodied with high luminance, low power consumption, high reliability and superior optical property by assembling a transistor block having high electron mobility. And the fabricating method of the present invention enables to make efficiently an AM-LED display apparatus at room temperature in a short time by using different shapes of receptor and block depending on the function of a transistor and/or on the color of an LED.
摘要翻译：提供一种有源矩阵LED显示装置及其制造方法。有源矩阵LED显示装置能够通过在底层上形成布线并且通过每个共晶层将每个块的组合分成每个根据每个色素单元形成的每个晶体管块接收器和/或每个LED块接收器来使像素小型化，并且通过组装具有高电子迁移率的晶体管块，具有高亮度，低功耗，高可靠性和优异的光学性能。本发明的制造方法能够根据晶体管的功能和/或LED的颜色，通过使用不同形状的接收器和块来在短时间内在室温下有效地制造AM-LED显示装置。

4. 发明授权

US09087922B2 Semiconductor devices having vertical device and non-vertical device and methods of forming the same 有权
标题翻译：具有垂直装置和非垂直装置的半导体装置及其形成方法
公开(公告)号：US09087922B2
公开(公告)日：2015-07-21
申请号：US13412760
申请日：2012-03-06
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8234 , H01L27/092 , H01L27/11
CPC分类号： H01L27/1104 , H01L21/823487 , H01L21/823885 , H01L27/092 , H01L29/7827
摘要： In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.
摘要翻译：在半导体器件中，垂直晶体管包括：衬底上的第一扩散区; 在所述第一扩散区域上的沿垂直方向延伸的沟道区域; 沟道区上的第二扩散区; 以及在沟道区的侧壁处和绝缘的栅电极。水平晶体管位于衬底上，水平晶体管包括：在衬底上的第一扩散区和第二扩散区，彼此间隔开; 在所述第一扩散区域和所述第二扩散区域之间的衬底上的沟道区域; 以及沟道区上的栅极，并与沟道区隔离。垂直晶体管的栅电极的一部分和水平晶体管的栅电极的一部分在垂直方向上相对于衬底处于相同的垂直位置。

5. 发明授权

US08455309B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08455309B2
公开(公告)日：2013-06-04
申请号：US13347361
申请日：2012-01-10
申请人： Song-Ju Lee , Jeong Soo Park , Byung-Gook Park , Hyun Woo Kim
发明人： Song-Ju Lee , Jeong Soo Park , Byung-Gook Park , Hyun Woo Kim
IPC分类号： H01L33/08
CPC分类号： H01L29/66356 , H01L29/7391
摘要： A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.
摘要翻译：一种技术能够简化在形成隧道场效应晶体管（TFET）结构中制造非对称器件的工艺。一种制造半导体器件的方法，包括在半导体衬底上形成导电图案，将导电图案作为掩模注入杂质离子，以在半导体衬底中形成第一结区，在导电图案上形成平坦化的第一绝缘膜，第一接合区域，蚀刻导电图案的顶部以暴露第一绝缘膜的侧壁，在布置在导电图案上的第一绝缘膜的侧壁处形成间隔物，用间隔物蚀刻导电图案作为蚀刻掩模，形成栅极图案，并且以栅极图案作为掩模在半导体衬底中形成第二结区域。

6. 发明授权

US08354708B2 Methods of forming and operating semiconductor device 有权
标题翻译：半导体器件的形成和操作方法
公开(公告)号：US08354708B2
公开(公告)日：2013-01-15
申请号：US13087643
申请日：2011-04-15
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

7. 发明授权

US07906397B2 Methods of fabricating nonvolatile semiconductor memory devices including a plurality of stripes having impurity layers therein 有权
标题翻译：制造包括其中具有杂质层的多个条纹的非易失性半导体存储器件的方法
公开(公告)号：US07906397B2
公开(公告)日：2011-03-15
申请号：US12410010
申请日：2009-03-24
申请人： Ki-whan Song , Byung-Gook Park
发明人： Ki-whan Song , Byung-Gook Park
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.
摘要翻译：非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个并且形成连接柱子并跨越字线上方的位线。

8. 发明授权

US07564084B2 Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的双栅极动态随机存取存储器件及其制造方法
公开(公告)号：US07564084B2
公开(公告)日：2009-07-21
申请号：US11513945
申请日：2006-08-31
申请人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park , Hoon Jeong
发明人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park , Hoon Jeong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/10844 , H01L27/10885 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.
摘要翻译：动态随机存取存储器（DRAM）器件具有双栅极垂直沟道晶体管。该器件包括柱形有源图案，其包括与半导体衬底接触的源极区域，形成在漏极区域上的漏极区域以及形成在源极和漏极区域之间的沟道区域。活动图案设置在单元阵列区域中。在有源图案上，位线布置成沿着一个方向连接漏极区域。在活动图案之间，字线被布置成与位线相交。盖子绝缘膜介于字线和有源图案之间。

9. 发明申请

US20070051994A1 Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的双栅极动态随机存取存储器件及其制造方法
公开(公告)号：US20070051994A1
公开(公告)日：2007-03-08
申请号：US11513945
申请日：2006-08-31
申请人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park , Hoon Jeong
发明人： Ki-Whan Song , Jong-Duk Lee , Byung-Gook Park , Hoon Jeong
IPC分类号： H01L29/94
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/10844 , H01L27/10885 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.
摘要翻译：动态随机存取存储器（DRAM）器件具有双栅极垂直沟道晶体管。该器件包括柱形有源图案，其包括与半导体衬底接触的源极区域，形成在漏极区域上的漏极区域以及形成在源极和漏极区域之间的沟道区域。活动图案设置在单元阵列区域中。在有源图案上，位线布置成沿着一个方向连接漏极区域。在活动图案之间，字线被布置成与位线相交。盖子绝缘膜介于字线和有源图案之间。

10. 发明申请

US20130102114A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130102114A1
公开(公告)日：2013-04-25
申请号：US13347361
申请日：2012-01-10
申请人： Song-Ju LEE , Jeong Soo Park , Byung-Gook Park , Hyun Woo Kim
发明人： Song-Ju LEE , Jeong Soo Park , Byung-Gook Park , Hyun Woo Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66356 , H01L29/7391
摘要： A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.
摘要翻译：一种技术能够简化在形成隧道场效应晶体管（TFET）结构中制造非对称器件的工艺。一种制造半导体器件的方法，包括在半导体衬底上形成导电图案，将导电图案作为掩模注入杂质离子，以在半导体衬底中形成第一结区，在导电图案上形成平坦化的第一绝缘膜，第一接合区域，蚀刻导电图案的顶部以暴露第一绝缘膜的侧壁，在布置在导电图案上的第一绝缘膜的侧壁处形成间隔物，用间隔物蚀刻导电图案作为蚀刻掩模，形成栅极图案，并且以栅极图案作为掩模在半导体衬底中形成第二结区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式