专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090163023A1 Phase change memory and method of fabricating the same 失效
标题翻译：相变记忆及其制造方法
公开(公告)号：US20090163023A1
公开(公告)日：2009-06-25
申请号：US12314884
申请日：2008-12-18
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L21/44
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

2. 发明授权

US08164079B2 Phase change memory 有权
标题翻译：相变记忆
公开(公告)号：US08164079B2
公开(公告)日：2012-04-24
申请号：US13092725
申请日：2011-04-22
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L47/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

3. 发明申请

US20110193047A1 PHASE CHANGE MEMORY 有权
标题翻译：相变记忆
公开(公告)号：US20110193047A1
公开(公告)日：2011-08-11
申请号：US13092725
申请日：2011-04-22
申请人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

4. 发明申请

US20120175580A1 VARIABLE RESISTANCE MEMORY 审中-公开
标题翻译：可变电阻记忆
公开(公告)号：US20120175580A1
公开(公告)日：2012-07-12
申请号：US13430042
申请日：2012-03-26
申请人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

5. 发明授权

US07932102B2 Phase change memory and method of fabricating the same 失效
标题翻译：相变记忆及其制造方法
公开(公告)号：US07932102B2
公开(公告)日：2011-04-26
申请号：US12314884
申请日：2008-12-18
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L21/00 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

6. 发明申请

US20080291652A1 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE 有权
标题翻译：半导体封装及其形成方法，印刷电路板和电子器件
公开(公告)号：US20080291652A1
公开(公告)日：2008-11-27
申请号：US12124915
申请日：2008-05-21
申请人： Mu-Seob Shin , Byung-Seo Kim , Min-Young Son , Min-Keun Kwak
发明人： Mu-Seob Shin , Byung-Seo Kim , Min-Young Son , Min-Keun Kwak
IPC分类号： H05K7/00
CPC分类号： H01L21/565 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/105 , H01L2224/05553 , H01L2224/06136 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/078 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess.
摘要翻译：提供一种半导体封装及其形成方法，以及PCB（印刷电路板）。所述半导体封装包括：PCB，其在其大致中央部分包括狭缝，所述PCB包括上表面和下表面; 安装在PCB的上表面上的半导体芯片; 上模制层，设置在上表面并覆盖半导体芯片; 以及填充所述狭缝并覆盖所述PCB的下表面的一部分的下成型层，其中所述PCB包括在其侧表面处的连接凹部，并且所述上成型层和所述下成型层彼此接触连接凹槽。

7. 发明授权

US07453794B2 Channel estimation and synchronization with preamble using polyphase code 失效
标题翻译：使用多相码的信道估计和前同步码同步
公开(公告)号：US07453794B2
公开(公告)日：2008-11-18
申请号：US10737339
申请日：2003-12-16
申请人： Yuguang Fang , Byung-Seo Kim
发明人： Yuguang Fang , Byung-Seo Kim
IPC分类号： H04J11/00
CPC分类号： H04L27/2656 , H04L5/0007 , H04L5/0048 , H04L25/0204 , H04L25/0226 , H04L27/2605 , H04L27/2613 , H04L27/2662
摘要： A preamble for an OFDM signal synchronizes (104) and estimates (106) the sub-channels with only one code. One polyphase code sequence is used repeatedly for the preamble. The preamble is spread out over the bandwidth, which is the same as an OFDM symbol in the frequency domain and has good autocorrelation characteristics in the time domain. All OFDM signals are added with this preamble at the beginning of the OFDM signal and transmitted on the channel at a transmitter (50). At the receiving end, the receiver (100) first does the autocorrelation process to find out a peak value for synchronization in the time domain. Then, since the polyphase code is known at the receiver, the signal to noise ratio for each sub-carrier is calculated in the frequency domain and smoothed using the normal (Gaussian) distribution to provide the channel estimation. Since the synchronization and channel estimation are processed with a single preamble, the overhead for these two functions is significantly reduced.
摘要翻译： OFDM信号的前导码同步（104）并仅使用一个码估计（106）子信道。对于前同步码重复使用一个多相码序列。前导码在带宽上扩展，与频域中的OFDM符号相同，并且在时域中具有良好的自相关特性。所有OFDM信号在OFDM信号的开始处与该前同步码相加，并在发射机（50）的信道上发送。在接收端，接收机（100）首先进行自相关处理，以找出在时域中同步的峰值。然后，由于在接收机处已知多相码，所以在频域中计算每个子载波的信噪比并使用正态（高斯）分布进行平滑，以提供信道估计。由于使用单个前同步码来处理同步和信道估计，所以这两个功能的开销显着降低。

8. 发明申请

US20050111590A1 Multi-layer differential phase shift keying with bit-interleaved coded modulation and OFDM 失效
标题翻译：具有位交织编码调制和OFDM的多层差分相移键控
公开(公告)号：US20050111590A1
公开(公告)日：2005-05-26
申请号：US10721533
申请日：2003-11-25
申请人： Yuguang Fang , Byung-Seo Kim
发明人： Yuguang Fang , Byung-Seo Kim
IPC分类号： H04L27/20 , H04L27/22
CPC分类号： H04L27/205 , H04L27/2071 , H04L27/2075
摘要： An efficient system and method for modulation and demodulation to achieve a high data rate using Bit-Interleaved Coded Modulation and OFDM uses either a coherent or a non-coherent transmission scheme using differential modulation. In order to maintain a high data rate impervious to sudden phase changes, a communication system uses an efficient constellation having multiple rings with different sizes and modulation/demodulation schemes utilizing this constellation. In power line communications, the channel gain information is obtained easily at a receiver (100) while the phase information is not. Thus, the communication system uses an absolute magnitude and differential phase coding for modulation and demodulation of the signals.
摘要翻译：用于使用比特交错编码调制实现高数据速率的调制和解调的有效系统和方法使用差分调制使用相干或非相干传输方案。为了保持突发相位变化的高数据速率，通信系统使用具有不同大小的多个环的有效星座和利用该星座的调制/解调方案。在电力线通信中，在相位信息不是在接收器（100）处容易地获得信道增益信息。因此，通信系统使用绝对幅度和差分相位编码来进行信号的调制和解调。

9. 发明申请

US20050009261A1 Semiconductor memory device having resistor and method of fabricating the same 有权
标题翻译：具有电阻器的半导体存储器件及其制造方法
公开(公告)号：US20050009261A1
公开(公告)日：2005-01-13
申请号：US10911157
申请日：2004-08-02
申请人： Dong-Hwa Kwak , Byung-Seo Kim
发明人： Dong-Hwa Kwak , Byung-Seo Kim
IPC分类号： H01L21/108 , H01L21/8242 , H01L27/06 , H01L27/105 , H01L27/108 , H01L21/8238
CPC分类号： H01L27/10894 , H01L27/0629 , H01L27/105 , H01L27/10814 , H01L27/10882 , Y10S257/904
摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.
摘要翻译：提供一种在周边区域具有电阻器的半导体器件及其制造方法。在半导体基板上形成模层。图案化模具层以在模具层中形成第一模制孔和第二模制孔。存储节点层形成在模具层以及第一和第二模制孔中。存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

10. 发明授权

US07319254B2 Semiconductor memory device having resistor and method of fabricating the same 有权
标题翻译：具有电阻器的半导体存储器件及其制造方法
公开(公告)号：US07319254B2
公开(公告)日：2008-01-15
申请号：US10911157
申请日：2004-08-02
申请人： Dong-Hwa Kwak , Byung-Seo Kim
发明人： Dong-Hwa Kwak , Byung-Seo Kim
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L31/0392
CPC分类号： H01L27/10894 , H01L27/0629 , H01L27/105 , H01L27/10814 , H01L27/10882 , Y10S257/904
摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.
摘要翻译：提供一种在周边区域具有电阻器的半导体器件及其制造方法。在半导体基板上形成模层。图案化模具层以在模具层中形成第一模制孔和第二模制孔。存储节点层形成在模具层以及第一和第二模制孔中。存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式