专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130301350A1 Vertical Structure Nonvolatile Memory Device 审中-公开
标题翻译：垂直结构非易失性存储器件
公开(公告)号：US20130301350A1
公开(公告)日：2013-11-14
申请号：US13939912
申请日：2013-07-11
申请人： Byeong-In Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
发明人： Byeong-In Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
IPC分类号： H01L29/78 , G11C16/04
CPC分类号： H01L29/66666 , G11C16/0466 , G11C16/0483 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
摘要翻译：垂直结构的非易失性存储器件可以包括在衬底上沿垂直方向延伸的沟道层。存储单元串包括沿着沟道层的垂直侧壁在垂直方向上设置在基板上的多个晶体管。多个晶体管中的至少一个晶体管包括在晶体管的栅极中的至少一个凹部，至少一个包括沟道层的突起延伸到该凹槽中。

2. 发明申请

US20120003828A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20120003828A1
公开(公告)日：2012-01-05
申请号：US13173321
申请日：2011-06-30
申请人： Sung-Il Chang , Changseok Kang , Byeong-In Choe
发明人： Sung-Il Chang , Changseok Kang , Byeong-In Choe
IPC分类号： H01L21/28
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/4234 , H01L29/792
摘要： A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成包括牺牲层和选择栅极层的叠层结构，形成穿透层叠结构的穿透区域，在选择栅极层的侧壁上形成选择栅极绝缘层，穿透区域，并且在穿透区域中形成活性图案。该方法还包括通过去除牺牲层并在活性图案的暴露部分上形成信息存储层来暴露活性图案的一部分。

3. 发明授权

US07867883B2 Methods of fabricating non-volatile memory devices 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07867883B2
公开(公告)日：2011-01-11
申请号：US12146653
申请日：2008-06-26
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L21/425 , H01L29/06
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

4. 发明授权

US08804417B2 Nonvolatile memory device including dummy memory cell and program method thereof 有权
标题翻译：包括虚拟存储器单元的非易失性存储器件及其程序方法
公开(公告)号：US08804417B2
公开(公告)日：2014-08-12
申请号：US13157343
申请日：2011-06-10
申请人： Chan Park , Changseok Kang , Sung-Il Chang , Byeong-In Choe
发明人： Chan Park , Changseok Kang , Sung-Il Chang , Byeong-In Choe
IPC分类号： G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/22
CPC分类号： G11C16/10 , G11C16/3418
摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.
摘要翻译：一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

5. 发明申请

US20110305079A1 NONVOLATILE MEMORY DEVICE INCLUDING DUMMY MEMORY CELL AND PROGRAM METHOD THEREOF 有权
标题翻译：非易失性存储器件，包括DUMMY存储器单元及其程序方法
公开(公告)号：US20110305079A1
公开(公告)日：2011-12-15
申请号：US13157343
申请日：2011-06-10
申请人： Chan Park , Changseok Kang , Sung-Il Chang , Byeong-In Choe
发明人： Chan Park , Changseok Kang , Sung-Il Chang , Byeong-In Choe
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/3418
摘要： A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.
摘要翻译：一种包括虚拟存储单元的非易失性存储器件及其编程方法，其中非易失性存储器件包括一个虚拟存储单元和与该虚拟存储单元串联连接的多个存储单元。非易失性存储装置根据执行程序操作时的多个存储单元中的所选择的存储单元与虚拟存储单元之间的距离，设定提供给虚拟存储单元的电压。

6. 发明申请

US20110079838A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20110079838A1
公开(公告)日：2011-04-07
申请号：US12961678
申请日：2010-12-07
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

7. 发明申请

US20090001451A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090001451A1
公开(公告)日：2009-01-01
申请号：US12146653
申请日：2008-06-26
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

8. 发明授权

US08644074B2 Nonvolatile memory device, programming method thereof and memory system including the same 有权
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US08644074B2
公开(公告)日：2014-02-04
申请号：US13107139
申请日：2011-05-13
申请人： Sung-Il Chang , Changseok Kang , Chan Park , Byeong-In Choe
发明人： Sung-Il Chang , Changseok Kang , Chan Park , Byeong-In Choe
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/0483
摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.
摘要翻译：一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

9. 发明申请

US20110286274A1 NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US20110286274A1
公开(公告)日：2011-11-24
申请号：US13107139
申请日：2011-05-13
申请人： Sung-Il Chang , Changseok Kang , Chan Park , Byeong-In Choe
发明人： Sung-Il Chang , Changseok Kang , Chan Park , Byeong-In Choe
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/0483
摘要： A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.
摘要翻译：一种防止程序干扰的非易失性存储器件，其程序方法和包括非易失性存储器件和程序方法的存储器系统。非易失性存储器件包括存储单元阵列; 连接到存储单元阵列中的NAND串的第一和第二字线; 连接到NAND串的第三字线，第三字线设置在第一和第二字线之间; 温度传感器，被配置为测量所述非易失性存储装置的温度; 以及电压发生器，被配置为产生第一和第二通过电压和编程电压，并且根据测量的温度来控制第一和第二通过电压中的至少一个的电压电平。当执行编程操作时，将编程电压施加到第三字线，将第一通过电压施加到第一字线，将第二通过电压施加到第二字线。

10. 发明授权

US08737129B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US08737129B2
公开(公告)日：2014-05-27
申请号：US13355834
申请日：2012-01-23
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式