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1. 发明申请

US20080270743A1 System and Method for Achieving Enhanced Memory Access Capabilities 有权
标题翻译：实现增强内存访问功能的系统和方法
公开(公告)号：US20080270743A1
公开(公告)日：2008-10-30
申请号：US11741453
申请日：2007-04-27
申请人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
发明人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
IPC分类号： G06F9/26
CPC分类号： G06F12/0607 , G06F12/0817 , G06F13/1657
摘要： A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要翻译：公开了一种计算机系统，诸如处理器代理的相关组件和相关方法。在至少一个实施例中，计算机系统包括第一核心，包括第一存储器段的至少一个存储器设备和耦合到第一存储器段的第一存储器控制器。此外，计算机系统包括织物和至少一个处理器代理，至少间接耦合到第一核心和第一存储器段，并且还耦合到织物。相对于第一存储器段内的第一存储器位置的第一存储器的第一存储器请求通过至少一个处理器代理和结构进行到第一存储器控制器。

2. 发明授权

US07818508B2 System and method for achieving enhanced memory access capabilities 有权
标题翻译：实现增强内存访问功能的系统和方法
公开(公告)号：US07818508B2
公开(公告)日：2010-10-19
申请号：US11741453
申请日：2007-04-27
申请人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
发明人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
IPC分类号： G06F13/00
CPC分类号： G06F12/0607 , G06F12/0817 , G06F13/1657
摘要： A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要翻译：公开了一种计算机系统，诸如处理器代理的相关组件和相关方法。在至少一个实施例中，计算机系统包括第一核心，包括第一存储器段的至少一个存储器设备和耦合到第一存储器段的第一存储器控制器。此外，计算机系统包括织物和至少一个处理器代理，至少间接耦合到第一核心和第一存储器段，并且还耦合到织物。相对于第一存储器段内的第一存储器位置的第一存储器的第一存储器请求通过至少一个处理器代理和结构进行到第一存储器控制器。

3. 发明授权

US09690673B2 Single and double chip spare 有权
公开(公告)号：US09690673B2
公开(公告)日：2017-06-27
申请号：US14365191
申请日：2012-01-31
申请人： Gary Gostin , Erin A. Handgen
发明人： Gary Gostin , Erin A. Handgen
IPC分类号： G06F11/00 , G06F11/16 , G11C29/00 , G06F3/06 , G06F11/10
CPC分类号： G06F11/1666 , G06F3/0619 , G06F3/0658 , G06F3/0683 , G06F11/1064 , G06F11/1068 , G11C29/808
摘要： Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

4. 发明申请

US20150006977A1 SINGLE AND DOUBLE CHIP SPARE 有权
标题翻译：单和双芯片备件
公开(公告)号：US20150006977A1
公开(公告)日：2015-01-01
申请号：US14365191
申请日：2012-01-31
申请人： Gary Gostin , Erin A. Handgen
发明人： Gary Gostin , Erin A. Handgen
IPC分类号： G06F11/16 , G06F3/06
CPC分类号： G06F11/1666 , G06F3/0619 , G06F3/0658 , G06F3/0683 , G06F11/1064 , G06F11/1068 , G11C29/808
摘要： Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
摘要翻译：提供了克服内存故障的技术。存储器的一部分可以以单个芯片备用模式工作。当在存储器的该部分中检测到单个芯片中的错误时，存储器的该部分的区域可被转换为以双芯片备用模式工作。可以在单芯片和双芯片备用模式下访问存储器。

5. 发明授权

US5821950A Computer graphics system utilizing parallel processing for enhanced performance 失效
标题翻译：使用并行处理的计算机图形系统提高性能
公开(公告)号：US5821950A
公开(公告)日：1998-10-13
申请号：US634458
申请日：1996-04-18
申请人： Eric M. Rentschler , Monish S. Shah , Mary A. Matthews , Alan S. Krech, Jr. , Erin A. Handgen
发明人： Eric M. Rentschler , Monish S. Shah , Mary A. Matthews , Alan S. Krech, Jr. , Erin A. Handgen
IPC分类号： G06T1/20 , G06T15/00 , G06F15/80
CPC分类号： G06T15/005 , G06T1/20
摘要： A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.
摘要翻译：计算机图形系统包括多个几何加速器，用于处理表示图形原语的顶点数据并提供呈现数据。该系统包括响应于顶点数据流的分布器，用于分布到几何加速器顶点数据的块中，用于由几何加速器处理以提供重绘数据块。分配器生成指示每个顶点数据块的结束的块位的结尾。该系统还包括一个收集器，用于从每个几何加速器接收渲染数据的块，并且响应于块位的结尾将渲染数据的块组合成渲染数据流。渲染数据流和顶点数据流表示具有相同顺序的图形基元的序列。光栅化器响应于渲染数据流生成表示图形显示的像素数据。

6. 发明申请

US20110040950A1 TRANSLATION LOOK-ASIDE BUFFER 有权
标题翻译：翻译书面缓冲区
公开(公告)号：US20110040950A1
公开(公告)日：2011-02-17
申请号：US12989350
申请日：2008-05-21
申请人： Erin A. Handgen
发明人： Erin A. Handgen
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.
摘要翻译：描述了翻译后备缓冲器（TLB）。 TLB可以包括填充有指向虚拟到物理地址转换的集合（例如，表）的指针的存储器。响应于解决页面错误，存储器可以由例如页面错误逻辑填充。 TLB还可以包括用于接收虚拟地址的信号逻辑，并且选择性地提供未命中信号或指向虚拟到物理转换的集合的指针。在确定虚拟地址不与所存储的指针相关联时，信号可以提供未命中信号，并且可以在确定虚拟地址与指针相关联时提供指针。

7. 发明授权

US5222243A Sorting apparatus having plurality of registers with associated multiplexers and comparators for concurrently sorting and storing incoming data according to magnitude 失效
标题翻译：具有相关多路复用器和比较器的多个寄存器的分类设备，用于同时存储和存储根据扩展的入局数据
公开(公告)号：US5222243A
公开(公告)日：1993-06-22
申请号：US478126
申请日：1990-02-09
申请人： Randall D. Briggs , Erin A. Handgen
发明人： Randall D. Briggs , Erin A. Handgen
IPC分类号： G06F7/22 , G06F7/24
CPC分类号： G06F7/24
摘要： Apparatus for receiving and automatically storing data words according to magnitude is provided. A self-sorting stack embodying the invention comprises a sorting device comprising means for simultaneously comparing the incoming data with the contents of each stack register, and logic and switching means for automatically inserting the new data into the correct register on the stack while at the same time pushing the contents of that and subsequent registers down one location. The entire operation is performed in one clock cycle, the same as for a conventional nonsorting stack.

8. 发明授权

US08429376B2 Translation look-aside buffer 有权
标题翻译：翻译后备缓冲区
公开(公告)号：US08429376B2
公开(公告)日：2013-04-23
申请号：US12989350
申请日：2008-05-21
申请人： Erin A. Handgen
发明人： Erin A. Handgen
IPC分类号： G06F9/26 , G06F9/34
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.
摘要翻译：描述了翻译后备缓冲器（TLB）。 TLB可以包括填充有指向虚拟到物理地址转换的集合（例如，表）的指针的存储器。响应于解决页面错误，存储器可以由例如页面错误逻辑填充。 TLB还可以包括用于接收虚拟地址的信号逻辑，并且选择性地提供未命中信号或指向虚拟到物理转换的集合的指针。在确定虚拟地址不与所存储的指针相关联时，信号可以提供未命中信号，并且可以在确定虚拟地址与指针相关联时提供指针。

9. 发明授权

US08244983B2 Memory control systems with directory caches and methods for operation thereof 有权
标题翻译：具有目录缓存的内存控制系统及其操作方法
公开(公告)号：US08244983B2
公开(公告)日：2012-08-14
申请号：US11554383
申请日：2006-10-30
申请人： Erin A. Handgen
发明人： Erin A. Handgen
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0822 , Y02D10/13
摘要： A memory control system is provided with a directory cache and a memory controller. The directory cache has a plurality of directory cache entries configured to store information regarding copies of memory lines stored in a plurality of memory caches, wherein each directory cache entry has one or more bits configured to store an ownership state that indicates whether a corresponding master directory entry lacks a memory cache owner. The memory controller is configured to free for re-use ones of the directory cache entries by 1) accessing a particular directory entry, and 2) determining whether the ownership state of the particular directory cache entry indicates that a corresponding master directory entry lacks a memory cache owner. If so, the memory controller A) skips a master directory update process, and B) claims for re-use the particular directory cache entry.
摘要翻译：存储器控制系统具有目录缓存和存储器控制器。目录缓存具有多个目录缓存条目，其被配置为存储关于存储在多个存储器高速缓存中的存储器行的副本的信息，其中每个目录高速缓存条目具有被配置为存储指示是否相应的主目录的所有权状态的一个或多个位条目缺少内存缓存所有者。存储器控制器被配置为通过1）访问特定目录条目来释放重新使用目录缓存条目中的一个;以及2）确定特定目录高速缓存条目的所有权状态是否指示对应的主目录条目缺少存储器缓存所有者。如果是这样，则内存控制器A）跳过主目录更新过程，并且B）声明重新使用特定的目录缓存条目。

10. 发明申请

US20080059710A1 Directory caches, and methods for operation thereof 有权
标题翻译：目录缓存及其操作方法
公开(公告)号：US20080059710A1
公开(公告)日：2008-03-06
申请号：US11514549
申请日：2006-08-31
申请人： Erin A. Handgen , Leith L. Johnson
发明人： Erin A. Handgen , Leith L. Johnson
IPC分类号： G06F12/00
CPC分类号： G06F12/0826 , G06F12/082
摘要： A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.
摘要翻译：目录缓存被提供有多个目录条目，其被配置为存储关于存储在多个高速缓存中的存储器行的副本的信息。这些条目被划分为N个条目的集合，每个N个条目的集合可通过索引寻址。目录缓存还提供有缓存控制器。缓存控制器检索与对应于存储器线的索引相关联的一组N个条目，并且如果检索到的条目之一的标签部分对应于存储器行，则高速缓存控制器确定所检索的条目之一是否包含指示关于存储器线的信息被存储在所检索的条目中的至少第二个中。

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