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    • 1. 发明授权
    • Computer graphics system utilizing parallel processing for enhanced
performance
    • 使用并行处理的计算机图形系统提高性能
    • US5821950A
    • 1998-10-13
    • US634458
    • 1996-04-18
    • Eric M. RentschlerMonish S. ShahMary A. MatthewsAlan S. Krech, Jr.Erin A. Handgen
    • Eric M. RentschlerMonish S. ShahMary A. MatthewsAlan S. Krech, Jr.Erin A. Handgen
    • G06T1/20G06T15/00G06F15/80
    • G06T15/005G06T1/20
    • A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.
    • 计算机图形系统包括多个几何加速器,用于处理表示图形原语的顶点数据并提供呈现数据。 该系统包括响应于顶点数据流的分布器,用于分布到几何加速器顶点数据的块中,用于由几何加速器处理以提供重绘数据块。 分配器生成指示每个顶点数据块的结束的块位的结尾。 该系统还包括一个收集器,用于从每个几何加速器接收渲染数据的块,并且响应于块位的结尾将渲染数据的块组合成渲染数据流。 渲染数据流和顶点数据流表示具有相同顺序的图形基元的序列。 光栅化器响应于渲染数据流生成表示图形显示的像素数据。
    • 4. 发明申请
    • TRANSLATION LOOK-ASIDE BUFFER
    • 翻译书面缓冲区
    • US20110040950A1
    • 2011-02-17
    • US12989350
    • 2008-05-21
    • Erin A. Handgen
    • Erin A. Handgen
    • G06F12/10
    • G06F12/1027G06F2212/681G06F2212/684
    • A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.
    • 描述了翻译后备缓冲器(TLB)。 TLB可以包括填充有指向虚拟到物理地址转换的集合(例如,表)的指针的存储器。 响应于解决页面错误,存储器可以由例如页面错误逻辑填充。 TLB还可以包括用于接收虚拟地址的信号逻辑,并且选择性地提供未命中信号或指向虚拟到物理转换的集合的指针。 在确定虚拟地址不与所存储的指针相关联时,信号可以提供未命中信号,并且可以在确定虚拟地址与指针相关联时提供指针。
    • 6. 发明授权
    • Translation look-aside buffer
    • 翻译后备缓冲区
    • US08429376B2
    • 2013-04-23
    • US12989350
    • 2008-05-21
    • Erin A. Handgen
    • Erin A. Handgen
    • G06F9/26G06F9/34
    • G06F12/1027G06F2212/681G06F2212/684
    • A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.
    • 描述了翻译后备缓冲器(TLB)。 TLB可以包括填充有指向虚拟到物理地址转换的集合(例如,表)的指针的存储器。 响应于解决页面错误,存储器可以由例如页面错误逻辑填充。 TLB还可以包括用于接收虚拟地址的信号逻辑,并且选择性地提供未命中信号或指向虚拟到物理转换的集合的指针。 在确定虚拟地址不与所存储的指针相关联时,信号可以提供未命中信号,并且可以在确定虚拟地址与指针相关联时提供指针。
    • 7. 发明授权
    • Memory control systems with directory caches and methods for operation thereof
    • 具有目录缓存的内存控制系统及其操作方法
    • US08244983B2
    • 2012-08-14
    • US11554383
    • 2006-10-30
    • Erin A. Handgen
    • Erin A. Handgen
    • G06F12/00G06F12/08G06F13/00
    • G06F12/0822Y02D10/13
    • A memory control system is provided with a directory cache and a memory controller. The directory cache has a plurality of directory cache entries configured to store information regarding copies of memory lines stored in a plurality of memory caches, wherein each directory cache entry has one or more bits configured to store an ownership state that indicates whether a corresponding master directory entry lacks a memory cache owner. The memory controller is configured to free for re-use ones of the directory cache entries by 1) accessing a particular directory entry, and 2) determining whether the ownership state of the particular directory cache entry indicates that a corresponding master directory entry lacks a memory cache owner. If so, the memory controller A) skips a master directory update process, and B) claims for re-use the particular directory cache entry.
    • 存储器控制系统具有目录缓存和存储器控制器。 目录缓存具有多个目录缓存条目,其被配置为存储关于存储在多个存储器高速缓存中的存储器行的副本的信息,其中每个目录高速缓存条目具有被配置为存储指示是否相应的主目录的所有权状态的一个或多个位 条目缺少内存缓存所有者。 存储器控制器被配置为通过1)访问特定目录条目来释放重新使用目录缓存条目中的一个;以及2)确定特定目录高速缓存条目的所有权状态是否指示对应的主目录条目缺少存储器 缓存所有者。 如果是这样,则内存控制器A)跳过主目录更新过程,并且B)声明重新使用特定的目录缓存条目。
    • 9. 发明申请
    • Directory caches, and methods for operation thereof
    • 目录缓存及其操作方法
    • US20080059710A1
    • 2008-03-06
    • US11514549
    • 2006-08-31
    • Erin A. HandgenLeith L. Johnson
    • Erin A. HandgenLeith L. Johnson
    • G06F12/00
    • G06F12/0826G06F12/082
    • A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.
    • 目录缓存被提供有多个目录条目,其被配置为存储关于存储在多个高速缓存中的存储器行的副本的信息。 这些条目被划分为N个条目的集合,每个N个条目的集合可通过索引寻址。 目录缓存还提供有缓存控制器。 缓存控制器检索与对应于存储器线的索引相关联的一组N个条目,并且如果检索到的条目之一的标签部分对应于存储器行,则高速缓存控制器确定所检索的条目之一是否包含指示 关于存储器线的信息被存储在所检索的条目中的至少第二个中。
    • 10. 发明授权
    • Coherency directory updating in a multiprocessor computing system
    • 多处理器计算系统中的一致性目录更新
    • US07941610B2
    • 2011-05-10
    • US11413158
    • 2006-04-27
    • Erin A. HandgenPatrick Knebel
    • Erin A. HandgenPatrick Knebel
    • G06F12/00G06F13/00G06F13/28
    • G06F12/0817G06F2212/2542Y02D10/13
    • Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache including an entry for each of a plurality of coherency units, each coherency unit included in a memory block representing a contiguous portion of the plurality of memory resources. A controller is operably connected to the interconnect fabric. The controller is configured to control a portion of the plurality of memory resources, and has a comparator configured to identify whether a memory block is local. If the memory block is local, the controller is configured to set a state of the directory to exclusive for a write transaction. If the memory block is not local, the controller is configured to set the state to invalid for a write transaction.
    • 在多处理器计算系统中提供了一致性目录更新。 多个存储器资源具有目录,并且可操作地连接到互连结构。 电池可操作地连接到互连织物。 该小区具有包括多个相关性单元中的每一个的条目的高速缓存,每个相关性单元包括在表示多个存储器资源的连续部分的存储器块中。 控制器可操作地连接到互连结构。 控制器被配置为控制多个存储器资源的一部分,并且具有被配置为识别存储器块是否是本地的比较器。 如果内存块是本地的,则控制器被配置为将目录的状态设置为独占的写事务。 如果内存块不是本地的,则控制器被配置为将写入事务的状态设置为无效。