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1. 发明申请

US20050191825A1 Methods for transferring a thin layer from a wafer having a buffer layer 有权
标题翻译：从具有缓冲层的晶片转移薄层的方法
公开(公告)号：US20050191825A1
公开(公告)日：2005-09-01
申请号：US11032844
申请日：2005-01-10
申请人： Bruno Ghyselen , Cecile Aulnette , Benedite Osternaud , Nicolas Daval
发明人： Bruno Ghyselen , Cecile Aulnette , Benedite Osternaud , Nicolas Daval
IPC分类号： H01L21/02 , H01L21/20 , H01L21/762 , H01L27/12 , H01L21/00 , C30B1/00 , H01L21/30 , H01L21/36 , H01L21/46 , H01L21/84
CPC分类号： H01L21/76259 , H01L21/76254
摘要： A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone. The structure includes a portion of the buffer layer, the strained layer and the relaxed layer. Lastly; the method includes enriching the concentration of the at least one other semiconductor material in the relaxed layer of the structure.
摘要翻译：描述了从晶片转移半导体材料层的方法。晶片包括支撑基板和包括具有第一晶格参数的材料的缓冲层的上表面。在一个实施例中，该技术包括在缓冲层上生长应变层。应变层由具有与第一晶格参数基本不同的标称晶格参数的半导体材料制成，并且其生长到足够薄的厚度以避免其中的应变松弛。该方法还包括在应变层上生长松弛层。松弛层由硅制成，并且具有至少一种其它半导体材料的浓度，其具有基本上与第一晶格参数相同的标称晶格参数。该技术还包括在缓冲层中提供弱化区域，并提供能量以在弱化区域分离结构。该结构包括缓冲层的一部分，应变层和松弛层。最后; 该方法包括在结构的松弛层中富集至少一种其它半导体材料的浓度。

2. 发明申请

US20050070078A1 Indirect bonding with disappearance of bonding layer 失效
标题翻译：间接键合与粘结层消失
公开(公告)号：US20050070078A1
公开(公告)日：2005-03-31
申请号：US10753173
申请日：2004-01-06
申请人： Nicolas Daval , Bruno Ghyselen , Cecile Aulnette , Oliver Rayssac , Ian Cayrefourcq
发明人： Nicolas Daval , Bruno Ghyselen , Cecile Aulnette , Oliver Rayssac , Ian Cayrefourcq
IPC分类号： H01L21/20 , H01L21/762 , H01L21/22
CPC分类号： H01L21/76251 , H01L21/2007 , H01L21/76254 , Y10S438/933
摘要： The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.
摘要翻译：本发明提供一种在支撑基板上制造半导体材料薄层结构的方法。薄层从供体基底获得并且包括半导体材料的上层。该方法包括在上层上形成接受来自上层材料的元素的扩散的材料的接合层，将施主衬底从上层上形成接合层的一侧粘合到支撑衬底上并且将元件从上层扩散到接合层中以使结合层和上层中的元素的浓度均匀化。结果是结构的薄层通过粘合层连接到上层。

3. 发明申请

US20080132031A1 METHOD OF MANUFACTURING A SEMICONDUCTOR HETEROSTRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20080132031A1
公开(公告)日：2008-06-05
申请号：US11674392
申请日：2007-02-13
申请人： Cecile Aulnette , Christophe Figuet , Nicolas Daval
发明人： Cecile Aulnette , Christophe Figuet , Nicolas Daval
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
摘要翻译：一种半导体异质结构的制造方法，首先制造具有第一面内晶格参数的第一衬底的施主晶片，具有第二面内晶格参数的空间渐变缓冲层，以及半导体材料的应变平滑化层，具有第一和第二格子参数之间的值的第三平面晶格参数。顶层在未分级层上形成具有顶表面的半导体材料的顶层，任选具有位于顶表面上的表层，并具有等于或小于10纳米的厚度。接下来，其上具有绝缘体层的第二衬底的处理晶片与施主晶片接合，使得（a）把手晶片的绝缘体层直接接合到施主晶片顶层的顶表面上，或者（b）把手晶片的绝缘体层结合到表面层上。

4. 发明申请

US20070020947A1 Method of reducing roughness of a thick insulating layer 有权
标题翻译：降低厚绝缘层粗糙度的方法
公开(公告)号：US20070020947A1
公开(公告)日：2007-01-25
申请号：US11481701
申请日：2006-07-05
申请人： Nicolas Daval , Sebastien Kerdiles , Cecile Aulnette
发明人： Nicolas Daval , Sebastien Kerdiles , Cecile Aulnette
IPC分类号： H01L21/31
CPC分类号： H01L21/76254 , H01L21/31055 , H01L21/31116
摘要： A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate; treating the first substrate to form a zone of weakness beneath the insulator layer; and smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radio frequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate to the insulator layer and to a second substrate.
摘要翻译：一种通过在衬底上沉积绝缘体层来减小衬底上的绝缘体层的暴露表面的粗糙度的方法，其中绝缘体层包括与衬底相对的暴露的粗糙表面; 处理所述第一衬底以在所述绝缘体层下方形成弱化区; 以及通过暴露于室中的气体等离子体来平滑所述绝缘体层的暴露的粗糙表面。该室中含有大于0.25Pa但小于30Pa的压力的气体，并且使用射频发生器产生气体等离子体，所述射频发生器施加到绝缘体层，功率密度大于0.6W / cm 2，但小于10W / cm 2，持续至少10秒至小于200秒。衬底结合和层转移可以随后进行以将衬底的薄层转移到绝缘体层和第二衬底。

5. 发明申请

US20110183493A1 PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE 审中-公开
标题翻译：在基板上制造包含锗层的结构的方法
公开(公告)号：US20110183493A1
公开(公告)日：2011-07-28
申请号：US12937920
申请日：2009-06-12
申请人： Nicolas Daval , Oleg Kononchuk , Eric Guiot , Cecile Aulnette , Fabrice Lallement , Christophe Figuet , Didier Landru
发明人： Nicolas Daval , Oleg Kononchuk , Eric Guiot , Cecile Aulnette , Fabrice Lallement , Christophe Figuet , Didier Landru
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256
摘要： The present invention relates to a process for manufacturing a structure comprising a germanium layer (3) on a support substrate (1), characterised in that it comprises the following steps: (a) formation of an intermediate structure (10) comprising said support substrate (1), a silicon oxide layer (20) and said germanium layer (3), the silicon oxide layer (20) being in direct contact with the germanium layer (3), (b) application to said intermediate structure (10) of a heat treatment, in a neutral or reducing atmosphere, at a defined temperature and for a defined time, to diffuse at least part of the oxygen from the silicon oxide layer (20) through the germanium layer (3).
摘要翻译：本发明涉及一种用于制造包括在支撑衬底（1）上的锗层（3）的结构的方法，其特征在于包括以下步骤：（a）形成包含所述支撑衬底的中间结构（10）（1），氧化硅层（20）和所述锗层（3），氧化硅层（20）与锗层（3）直接接触，（b）施加到所述中间结构（10）在中性或还原性气氛中，在限定的温度下和在一定时间内进行热处理，以使至少部分氧从氧化硅层（20）扩散通过锗层（3）。

6. 发明申请

US20110140230A1 MANUFACTURE OF THIN SILICON-ON-INSULATOR (SOI) STRUCTURES 有权
标题翻译：薄硅绝缘体（SOI）结构的制造
公开(公告)号：US20110140230A1
公开(公告)日：2011-06-16
申请号：US12956547
申请日：2010-11-30
申请人： Nicolas Daval , Cecile Aulnette
发明人： Nicolas Daval , Cecile Aulnette
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/76256
摘要： The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.
摘要翻译：本发明涉及通过在施主衬底上形成第一蚀刻停止层来形成具有薄硅层的SOI结构的方法，在第一蚀刻停止层上形成第二蚀刻停止层，其中第二蚀刻停止层的材料层与第一蚀刻停止层的材料不同，优选通过外延在第二蚀刻停止层上形成薄硅层，并将中间结构结合到目标衬底，然后通过在第一蚀刻停止层中引发的分裂分离施主衬底蚀刻停止层，并去除蚀刻停止层的剩余材料以产生最终的ETSOI结构。本发明还涉及通过所述方法产生的ETSOI结构。

7. 发明授权

US09018678B2 Method for forming a Ge on III/V-on-insulator structure 有权
标题翻译：用于在III / V绝缘体上形成Ge的方法
公开(公告)号：US09018678B2
公开(公告)日：2015-04-28
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/786 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

8. 发明授权

US08367521B2 Manufacture of thin silicon-on-insulator (SOI) structures 有权
标题翻译：薄绝缘体上硅（SOI）结构的制造
公开(公告)号：US08367521B2
公开(公告)日：2013-02-05
申请号：US12956547
申请日：2010-11-30
申请人： Nicolas Daval , Cecile Aulnette
发明人： Nicolas Daval , Cecile Aulnette
IPC分类号： H01L21/46 , H01L29/06
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/76256
摘要： The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.
摘要翻译：本发明涉及通过在施主衬底上形成第一蚀刻停止层来形成具有薄硅层的SOI结构的方法，在第一蚀刻停止层上形成第二蚀刻停止层，其中第二蚀刻停止层的材料层与第一蚀刻停止层的材料不同，优选通过外延在第二蚀刻停止层上形成薄硅层，并将中间结构结合到目标衬底，然后通过在第一蚀刻停止层中引发的分裂分离施主衬底蚀刻停止层，并去除蚀刻停止层的剩余材料以产生最终的ETSOI结构。本发明还涉及通过所述方法产生的ETSOI结构。

9. 发明申请

US20120228672A1 METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE 有权
标题翻译：用于形成III / V型绝缘体结构的方法
公开(公告)号：US20120228672A1
公开(公告)日：2012-09-13
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/267 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

10. 发明申请

US20090023267A1 METHOD OF REDUCING ROUGHNESS OF A THICK INSULATING LAYER 有权
标题翻译：减少厚度绝缘层粗糙度的方法
公开(公告)号：US20090023267A1
公开(公告)日：2009-01-22
申请号：US12234280
申请日：2008-09-19
申请人： Nicolas Daval , Sebastien Kerdiles , Cecile Aulnette
发明人： Nicolas Daval , Sebastien Kerdiles , Cecile Aulnette
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/31055 , H01L21/31116
摘要： A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.
摘要翻译：一种通过在衬底上沉积绝缘体层来减小衬底上的绝缘体层的暴露表面的粗糙度的方法，其中绝缘体层包括与衬底相对的暴露的粗糙表面，然后通过暴露于室内的气体等离子体。该室包含大于0.25Pa但小于30Pa的压力的气体，并且使用射频发生器产生气体等离子体，所述射频发生器施加到绝缘体层的功率密度大于0.6W / cm 2但小于10W / cm2至少10秒至小于200秒。衬底接合和层转移可以随后进行以将衬底和绝缘体层的薄层转移到第二衬底。

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