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1. 发明授权

US09018678B2 Method for forming a Ge on III/V-on-insulator structure 有权
标题翻译：用于在III / V绝缘体上形成Ge的方法
公开(公告)号：US09018678B2
公开(公告)日：2015-04-28
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/786 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

2. 发明申请

US20120228672A1 METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE 有权
标题翻译：用于形成III / V型绝缘体结构的方法
公开(公告)号：US20120228672A1
公开(公告)日：2012-09-13
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/267 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

3. 发明申请

US20100289113A1 FABRICATION PROCESS OF A HYBRID SEMICONDUCTOR SUBSTRATE 有权
标题翻译：混合半导体衬底的制造工艺
公开(公告)号：US20100289113A1
公开(公告)日：2010-11-18
申请号：US12726800
申请日：2010-03-18
申请人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
发明人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L21/2007 , H01L21/187 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L27/1207
摘要： The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.
摘要翻译：本发明涉及一种制造混合半导体衬底的方法，包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和SeOI层在绝缘层和体半导体区域之间，其中SeOI区域和体半导体区域共享相同的基底; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。从而避免了混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

4. 发明授权

US09035474B2 Method for manufacturing a semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US09035474B2
公开(公告)日：2015-05-19
申请号：US12793515
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
IPC分类号： H01L23/544 , H01L21/762 , H01L21/18 , H01L21/20
CPC分类号： H01L21/76254 , H01L21/187 , H01L21/2007 , H01L21/76251
摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.
摘要翻译：本发明涉及一种制造半导体衬底的方法，特别是通过提供一个施主衬底和一个把手衬底来制造绝缘体上半导体衬底，通常形成一个或多个掺杂区域的图案，通常在处理衬底内部，然后附着例如通过分子结合施主衬底和处理衬底以获得施主手柄化合物。

5. 发明授权

US08058158B2 Hybrid semiconductor substrate including semiconductor-on-insulator region and method of making the same 有权
标题翻译：包括绝缘体上半导体区域的混合半导体衬底及其制造方法
公开(公告)号：US08058158B2
公开(公告)日：2011-11-15
申请号：US12726800
申请日：2010-03-18
申请人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
发明人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/425 , H01L21/70
CPC分类号： H01L21/2007 , H01L21/187 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L27/1207
摘要： A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.
摘要翻译：一种用于制造混合半导体衬底的方法包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和绝缘层上的SeOI层，以及体半导体区域，其中所述SeOI区域和所述体半导体区域共享相同的基底基板; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。因此，可以避免在混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

6. 发明申请

US20110241157A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：制造半导体基板的方法
公开(公告)号：US20110241157A1
公开(公告)日：2011-10-06
申请号：US12793515
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76254 , H01L21/187 , H01L21/2007 , H01L21/76251
摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.
摘要翻译：本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案，通过分子键合供体和手柄底物以获得供体 - 处理化合物。

7. 发明申请

US20120228689A1 WAFER WITH INTRINSIC SEMICONDUCTOR LAYER 有权
标题翻译：带内置半导体层的波形
公开(公告)号：US20120228689A1
公开(公告)日：2012-09-13
申请号：US13416739
申请日：2012-03-09
申请人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
发明人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
IPC分类号： H01L27/108 , H01L21/02 , H01L29/16 , H01L21/762
CPC分类号： H01L27/10894 , H01L21/76254 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L27/1207 , H01L29/66181
摘要： The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.
摘要翻译：本发明涉及通过在半导体衬底上设置掺杂层来制造晶片的方法; 在所述掺杂层上提供第一半导体层; 在所述第一半导体层上提供掩埋氧化物层; 以及在所述掩埋氧化物层上提供第二半导体层以形成具有掩埋氧化物层和所述掩埋氧化物层下方的掺杂层的晶片。本发明还涉及通过新方法生产的晶片。

8. 发明授权

US09177961B2 Wafer with intrinsic semiconductor layer 有权
标题翻译：具有本征半导体层的晶片
公开(公告)号：US09177961B2
公开(公告)日：2015-11-03
申请号：US13416739
申请日：2012-03-09
申请人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
发明人： Nicolas Daval , Cécile Aulnette , Bich-Yen Nguyen
IPC分类号： H01L21/02 , H01L27/108 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/66
CPC分类号： H01L27/10894 , H01L21/76254 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L27/1207 , H01L29/66181
摘要： The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.
摘要翻译：本公开涉及通过在半导体衬底上设置掺杂层来制造晶片的方法; 在所述掺杂层上提供第一半导体层; 在所述第一半导体层上提供掩埋氧化物层; 以及在所述掩埋氧化物层上提供第二半导体层以形成具有掩埋氧化物层和所述掩埋氧化物层下方的掺杂层的晶片。本公开还涉及通过新方法生产的晶片。

9. 发明授权

US08842945B2 Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates 有权
标题翻译：形成三维集成半导体系统的方法，包括光敏元件和绝缘体上半导体衬底
公开(公告)号：US08842945B2
公开(公告)日：2014-09-23
申请号：US13206299
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： G02B6/12 , H01L25/16 , H01L27/06 , H01L31/103
CPC分类号： H01L25/167 , G02B6/12002 , G02B6/12004 , H01L27/0688 , H01L27/1203 , H01L31/103 , H01L33/34 , H01L2924/0002 , H01L2924/00
摘要： Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
摘要翻译：三维集成的半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。光学互连可操作地耦合到光活性器件。半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

10. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

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