专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070083700A1 METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS MEMORY SYSTEM 有权
标题翻译：调整同步存储器系统性能的方法和装置
公开(公告)号：US20070083700A1
公开(公告)日：2007-04-12
申请号：US11609135
申请日：2006-12-11
申请人： Bruno Garlepp , Pak Chau , Kevin Donnelly , Clemenz Portmann , Donald Stark , Stefanos Sidiropoulos , Richard Barth , Paul Davis , Ely Tsern
发明人： Bruno Garlepp , Pak Chau , Kevin Donnelly , Clemenz Portmann , Donald Stark , Stefanos Sidiropoulos , Richard Barth , Paul Davis , Ely Tsern
IPC分类号： G06F13/28
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
摘要翻译：提供了一种用于调整存储器系统的性能的方法和装置。存储器系统包括主设备和从设备。存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。从设备还包括用于在从设备内调谐电路的装置，从而提高存储器系统的性能。

2. 发明申请

US20060120409A1 Calibrated data communication system and method 有权
公开(公告)号：US20060120409A1
公开(公告)日：2006-06-08
申请号：US11327213
申请日：2006-01-05
申请人： Jared Zerbe , Kevin Donnelly , Stefanos Sidiropoulos , Donald Stark , Mark Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno Garlepp , Tsyr-Chyang Ho , Benedict Lau
发明人： Jared Zerbe , Kevin Donnelly , Stefanos Sidiropoulos , Donald Stark , Mark Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno Garlepp , Tsyr-Chyang Ho , Benedict Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

3. 发明申请

US20060188051A1 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US20060188051A1
公开(公告)日：2006-08-24
申请号：US11406557
申请日：2006-04-18
申请人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
发明人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
IPC分类号： H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

4. 发明申请

US20060059299A1 Apparatus and method for pipelined memory operations 有权
公开(公告)号：US20060059299A1
公开(公告)日：2006-03-16
申请号：US11270251
申请日：2005-11-08
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

5. 发明申请

US20070140035A1 Apparatus and Method for Pipelined Memory Operations 有权
标题翻译：流水线存储器操作的装置和方法
公开(公告)号：US20070140035A1
公开(公告)日：2007-06-21
申请号：US11675054
申请日：2007-02-14
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.
摘要翻译：半导体存储器件具有包括至少八个动态随机存取存储单元组和耦合到存储器核的内部数据总线的存储器核心。内部数据总线从存储器核心的选定组接收多个数据位。半导体存储器件还包括从外部接收半导体存储器件的读取命令的第一接口和用于输出多个数据位的第一和第二子集的第二接口。在外部时钟信号的第一阶段期间输出第一子集，并且在外部时钟信号的第二阶段期间输出第二子集。第一阶段包括第一边缘转变，第二阶段包括第二边缘过渡。第二边缘转变是相对于第一边缘转变的相反边缘转变。

6. 发明申请

US20080002516A1 Memory Device Having a Delay Locked Loop and Multiple Power Modes 审中-公开
标题翻译：具有延迟锁定环路和多个功率模式的存储器件
公开(公告)号：US20080002516A1
公开(公告)日：2008-01-03
申请号：US11856661
申请日：2007-09-17
申请人： Ely Tsern , Richard Barth , Craig Hampel , Donald Stark
发明人： Ely Tsern , Richard Barth , Craig Hampel , Donald Stark
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the delay locked loop circuit and the clock receiver circuit are turned on. Power consumption in the first power mode is less than that consumed while in an active mode. In a second power mode, the delay locked loop circuit is turned off. The memory is configured to receive a command that specifies a power down mode, to turn off the delay locked loop circuit in response to the command that specifies the power down mode, and to operate the memory device in a standby power mode. The delay locked loop circuit and the clock receiver circuit are turned on in a standby mode.
摘要翻译：单芯片动态随机存取存储器具有存储核心，包括动态随机存取存储器单元和用于接收外部时钟信号的时钟接收器电路。延迟锁定环电路耦合到时钟接收器电路。在第一功率模式中，延迟锁定环电路和时钟接收器电路被接通。在第一个功率模式下的功耗小于活动模式时消耗的功耗。在第二功率模式中，延迟锁定环电路被关断。存储器被配置为接收指定掉电模式的命令，以响应于指定掉电模式的命令来关闭延迟锁定环电路，并且在待机电源模式下操作存储器件。延迟锁定环电路和时钟接收器电路在待机模式下导通。

7. 发明申请

US20050180255A1 Memory device having a read pipeline and a delay locked loop 有权
标题翻译：具有读取流水线和延迟锁定环路的存储器件
公开(公告)号：US20050180255A1
公开(公告)日：2005-08-18
申请号：US11107504
申请日：2005-04-15
申请人： Ely Tsern , Richard Barth , Craig Hampel , Donald Stark
发明人： Ely Tsern , Richard Barth , Craig Hampel , Donald Stark
IPC分类号： G06F1/32 , G06F9/38 , G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。时钟接收器电路接收外部时钟信号。控制接口接收指定对存储器件的读取操作的命令。数据接口在存储器件和外部信号线组之间传送数据。延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。读取管线电路将从存储器核心访问的读取数据提供给数据接口。响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。

8. 发明授权

US07913104B1 Method and apparatus for receive channel data alignment with minimized latency variation 有权
标题翻译：用于以最小的延迟变化接收信道数据对准的方法和装置
公开(公告)号：US07913104B1
公开(公告)日：2011-03-22
申请号：US11974309
申请日：2007-10-12
申请人： Warren E. Cory , Donald Stark , Dean Liu , Clemenz Portmann
发明人： Warren E. Cory , Donald Stark , Dean Liu , Clemenz Portmann
IPC分类号： G06F1/04 , G06F1/00 , H04L7/00
CPC分类号： H04J3/0685 , G06F1/10 , H04J3/062
摘要： Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.
摘要翻译：通过利用相同的字节时钟信号，在接收机的整个数据字节处理逻辑中保持千兆位接收器内的数据和时钟同步。用于对接收到的串行数据流进行反序列化的反序列化时钟信号与物理编码子层（PCS）中使用的分布式字节时钟信号相位相关，从而建立跨物理介质连接（PMA）和PCS层的可靠数据传输千兆接收机，同时保持已知的固定延迟。导出的位时钟信号和字节时钟信号之间的相位关系以在每个数据字节内实现粗略数据对齐而不影响等待时间的方式移位。相反，粗略数据对齐与数据对齐切换过程相结合，以最小化延迟变化来减少数据对齐粒度。

9. 发明申请

US20070242532A1 Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time 有权
标题翻译：具有基于读响应时间的延迟写时序的集成电路存储器件
公开(公告)号：US20070242532A1
公开(公告)日：2007-10-18
申请号：US11692159
申请日：2007-03-27
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： G11C7/10 , G06F13/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.
摘要翻译：集成电路存储器件包括第一组引脚和存储器核。第一组引脚使用时钟信号接收写入命令和读取命令。控制信息在接收到写入命令之后经过预定的延迟时间之后响应写入命令被发出，控制信息在存储器件中启动写入操作。第二组引脚在从接收到读命令之后发生第一延迟时间后输出读数据。第二组引脚的每个引脚在时钟信号的时钟周期期间输出两位读取数据。第二组引脚还在接收到写入命令之后延迟了第二个延迟时间之后也接收到写入数据。第二延迟时间基于第一延迟时间。

10. 发明申请

US20070159912A1 Integrated Circuit Memory Device with Delayed Write Command Processing 有权
标题翻译：具有延迟写命令处理的集成电路存储器件
公开(公告)号：US20070159912A1
公开(公告)日：2007-07-12
申请号：US11681384
申请日：2007-03-02
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： G06F13/28 , G11C8/00 , G11C7/00 , G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.
摘要翻译：具有延迟写入命令处理的集成电路存储器件包括耦合到存储器核心的第一组引脚，第一组引脚以接收列地址的行地址。耦合到存储器核心的第二组引脚用于接收感测命令，后接写入命令。感测命令指定感测由行地址识别的一行存储器单元，并且写入命令指定存储器件接收写入数据并将写入数据存储在由列地址标识的列位置处。在从第二组引脚接收到写命令之后第一个延迟发生之后，写入命令在内部发布到存储器件中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式