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1. 发明授权

US5978262A Circuit and method of latching a bit line in a non-volatile memory 失效
标题翻译：在非易失性存储器中锁存位线的电路和方法
公开(公告)号：US5978262A
公开(公告)日：1999-11-02
申请号：US9290
申请日：1998-01-20
申请人： Alexis Marquot , Jean-Claude Tarbouriech , Paul Dechamps
发明人： Alexis Marquot , Jean-Claude Tarbouriech , Paul Dechamps
IPC分类号： G11C16/10 , G11C16/12 , G11C16/14
CPC分类号： G11C16/10 , G11C16/12
摘要： A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38, 44) each having outputs respectively coupled to bit lines (50, 54, 56), and control inputs coupled to a common control line (132). The bit lines each include a latch (60, 62, 64) that is set to provide a programming voltage (VPP) during write mode. The bit lines have serial switches (78, 80, 82) that break continuity when writing to the latches. The bit line latches are made transparent to the bit lines during read mode. The common control line is coupled through a programming transistor (130) to an erase line (72). The erase line must be driven to a programming voltage during erase mode. The erase line uses one of the bit line latches to provide its programming voltage.
摘要翻译：便携式数据载体（10）体现了具有EEPROM（24）的集成电路（12）。 EEPROM具有多行存储单元（32,38,44），每行存储单元具有分别耦合到位线（50,54,56）的输出和耦合到公共控制线（132）的控制输入。位线各自包括被设置为在写入模式期间提供编程电压（VPP）的锁存器（60,62,64）。位线具有串行开关（78,80,82），可在写入锁存器时断开连续性。在读取模式期间，位线锁存器对位线是透明的。公共控制线通过编程晶体管（130）耦合到擦除线（72）。在擦除模式下，必须将擦除线驱动到编程电压。擦除线使用位线锁存器之一来提供其编程电压。

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