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1. 发明授权

US4777588A General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance 失效
标题翻译：通用寄存器文件优化用于进行内部寄存器分配，过程调用和多任务性能
公开(公告)号：US4777588A
公开(公告)日：1988-10-11
申请号：US771311
申请日：1985-08-30
申请人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
发明人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/30 , G06F9/34 , G06F9/40 , G06F9/46 , G06F9/48 , G06F12/14
CPC分类号： G06F9/468 , G06F12/1458 , G06F9/4425 , G06F9/462
摘要： A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.
摘要翻译：公开了一种适用于精简指令集计算机（RISC）的指令处理器所使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。寄存器文件通过动态地提供两个过程可访问的重叠寄存器来促进过程之间的参数传递。每个过程也有一组分配给它的“本地”寄存器，不能从其他过程访问。寄存器文件被分成多个块，并且保护寄存器存储一个单词，其禁止特定过程或任务访问某些块。以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，从而保持每个任务的完整性，而不是在其他任务中发生不希望的变化。

2. 发明授权

US4777587A System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses 失效
标题翻译：在具有相对，绝对，间接和陷阱地址的管道中处理单周期分支指令的系统
公开(公告)号：US4777587A
公开(公告)日：1988-10-11
申请号：US771327
申请日：1985-08-30
申请人： Brian W. Case , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
发明人： Brian W. Case , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/32 , G06F9/38 , G06F9/48 , G06F9/00 , G06F9/42
CPC分类号： G06F9/30058 , G06F9/3842
摘要： An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.
摘要翻译：适用于简化指令集计算机的指令处理器采用在单个处理器周期中执行条件分支的指令流水线。处理器将分支条件视为常规指令操作数，而不是单独条件代码寄存器中的特殊情况。条件位和分支目标地址确定要获取哪个指令，分支在执行下一条指令之前不起作用。以这种方式，不需要在流水线中物理地跟随分支指令的指令的替换，并且分支发生在分配给它的流水线的单个周期内。一个简单的电路实现这种延迟分支方法。结合处理器的计算机容易地执行用于子程序，中断和陷阱的调用的特殊处理技术。

3. 发明授权

US4734852A Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor 失效
标题翻译：在精简指令集处理器上执行指令并行执行存储数据引用的机制
公开(公告)号：US4734852A
公开(公告)日：1988-03-29
申请号：US771435
申请日：1985-08-30
申请人： William M. Johnson , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
发明人： William M. Johnson , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3834
摘要： A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.
摘要翻译：实现与指令执行并行执行存储数据引用的机制的简单架构。该架构特别适用于简化指令集计算机（RISC），并采用通道地址寄存器来存储主存储器加载或存储地址，临时存储来自存储操作的数据的通道数据寄存器和通道控制寄存器，在加载操作的情况下，包含控制信息，包括在文件中加载的寄存器的编号。该数字用于检测要加载的数据的指令依赖性。如果负载所需的数据尚不可用，则逻辑电路将暂停进一步的指令处理。数据输入寄存器用于存储负载数据，直到指令执行周期可用于将其写回寄存器文件。逻辑电路在写入之前检测数据的存储，以便有效地替换寄存器文件位置。在页面故障期间，保存通道地址，通道数据和通道控制寄存器的内容，以允许页面故障恢复。

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