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1. 发明授权

US09065564B2 World-wide, wide-band, low-latency, mobile internet and system therefor 有权
标题翻译：全球范围内，宽带，低延迟，移动互联网及其系统
公开(公告)号：US09065564B2
公开(公告)日：2015-06-23
申请号：US13573794
申请日：2012-10-03
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： H04B10/00 , H04B10/118
CPC分类号： H04B7/195 , H04B7/18523 , H04B10/118
摘要： A communication system for providing world-wide, mobile Internet communication to a plurality of users and a method therefore. The system includes ground-based, multi-channel, radio frequency transmitting and receiving broadcasting grids that are capable of providing content to multiple users via cell towers and low-altitude, optical transmitting and receiving satellites that are in optical communication with the ground-based, multi-channel, RF transmitting and receiving broadcasting grids. The method includes transmitting optical and/or RF signals between at least one of the ground-based, multi-channel, RF transmitting and receiving broadcasting grids and at least one of the low-altitude, optical transmitting and receiving satellites.
摘要翻译：一种用于向多个用户提供世界范围的移动因特网通信的通信系统及其方法。该系统包括基于地面，多通道，射频发射和接收的广播网格，能够通过经由小区塔和与地面光通信的低空，光发射和接收卫星向多个用户提供内容，多通道，射频发射和接收广播电网。该方法包括在地面，多声道，RF发射和接收广播网格中的至少一个和低空，光发射和接收卫星中的至少一个之间传输光信号和/或RF信号。

2. 发明授权

US07739003B2 Method of determining and controlling the inertial attitude of a spinning, artificial satellite and systems therefor 失效
标题翻译：确定和控制旋转，人造卫星及其系统的惯性姿态的方法
公开(公告)号：US07739003B2
公开(公告)日：2010-06-15
申请号：US11818723
申请日：2007-06-15
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： G06F7/00 , B64G1/36
CPC分类号： B64G1/361 , B64G1/281 , G01S3/7862 , G05D1/0883
摘要： A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information. The method and apparatus include steps and means for selecting preferably three astronomical objects using a histogram method and determining a square of a first radius (R12) of a track of a first astronomical object; determining a square of a second radius (R22) of a track of a second astronomical object; determining a square of a third radius (R32) of a track of a third astronomical object; determining the inertial attitude of the spin axis using the squares of the first, second, and third radii (R12, R22, and R32) to calculate pitch, yaw, and roll rate; determining a change in the pitch and yaw of the artificial satellite; and controlling on-board generated current flow to various orthogonally-disposed current-carrying loops to act against the Earth's magnetic field and to apply gyroscopic precession to the spinning satellite to correct and maintain its optimum inertial attitude.
摘要翻译：用于在不使用一套惯性陀螺仪的情况下确定和控制旋转人造卫星的惯性姿态的方法和装置。该方法和装置通过跟踪地球黄道附近的三个天文物体和卫星和/或星形跟踪器的自旋轴进行操作并处理轨道信息。所述方法和装置包括使用直方图方法优选地选择三个天文物体并且确定第一天文物体的轨道的第一半径（R12）的平方的步骤和装置; 确定第二天文物体的轨道的第二半径（R22）的平方; 确定第三天文物体的轨道的第三半径（R32）的平方; 使用第一，第二和第三半径（R12，R22和R32）的平方来确定旋转轴的惯性姿态来计算俯仰，偏航和滚动速率; 确定人造卫星的俯仰和偏航的变化; 并且控制板上产生的电流流向各种正交布置的载流回路，以对地球的磁场起作用，并对旋转卫星施加陀螺进动，以校正和保持其最佳惯性姿态。

3. 发明授权

US06577929B2 Miniature attitude sensing suite 有权
标题翻译：微型姿态感应套件
公开(公告)号：US06577929B2
公开(公告)日：2003-06-10
申请号：US10058964
申请日：2002-01-28
申请人： William M. Johnson , Howard Musoff , Darryl G. Sargent , Jerold P. Gilmore , Cornelius J. Dennehy
发明人： William M. Johnson , Howard Musoff , Darryl G. Sargent , Jerold P. Gilmore , Cornelius J. Dennehy
IPC分类号： G06F700
CPC分类号： B64G1/361 , B64G1/281 , B64G1/288 , B64G1/36 , B64G1/38
摘要： The present invention provides methods of and apparatus for determining the inertial attitude of an aerospace vehicle. In one embodiment, the invention provides a rotational astronomical object-sighting concept to determine the inertial attitude of an axis of the aerospace vehicle without the star identification or dragback. In another embodiment, the invention provides an attitude measurement apparatus comprising a high sensitivity optical sensor and a low power inertial sensor.
摘要翻译：本发明提供用于确定航空航天器的惯性姿态的方法和装置。在一个实施例中，本发明提供了一种旋转天文观测概念，用于确定航空航天车辆的轴的惯性姿态，而没有星号识别或回退。在另一个实施例中，本发明提供一种包括高灵敏度光学传感器和低功率惯性传感器的姿态测量装置。

4. 发明授权

US06192462B1 Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache 失效
标题翻译：超标量微处理器包括加载/存储单元，解码单元和重排序缓冲器，用于检测访问堆栈高速缓存和数据高速缓存之间的依赖关系
公开(公告)号：US06192462B1
公开(公告)日：2001-02-20
申请号：US09162419
申请日：1998-09-28
申请人： Thang M. Tran , David B. Witt , William M. Johnson
发明人： Thang M. Tran , David B. Witt , William M. Johnson
IPC分类号： G06F938
CPC分类号： G06F9/30167 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is provided within the microprocessor. The dependency checking structure compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage. The comparator circuits used to perform the comparison are configured to compare a field of address bits instead of the entire address, reducing the size while still maintaining accurate dependency checking by qualifying the resulting comparison signals with an indication that both addresses hit in the same storage location within the stack cache.
摘要翻译：提供了一种超标量微处理器，其保持从指令处理流水线的不同阶段访问的一对缓存之间的一致性。在微处理器内提供依赖检查结构。依赖性检查结构将从指令处理流水线的执行阶段执行的存储器访问与从解码级执行的存储器访问进行比较。解码级对堆栈高速缓存执行存储器访问，而执行级通过间接寻址将其访问（通过间接寻址形成的地址）执行到堆栈高速缓存和数据高速缓存。如果由执行级执行的读取存储器访问取决于由解码级执行的写存储器访问，则读存储器访问被停止，直到写存储器访问完成。如果由解码级执行的读取存储器访问取决于由执行级执行的写入存储器访问，则刷新与读取的存储器访问和后续指令相关联的指令。在一对缓存之间保持数据一致性，同时允许从解码级执行堆栈相对访问。用于执行比较的比较器电路被配置为比较地址位的字段而不是整个地址，减小大小，同时仍然通过将所得到的比较信号限定在相同存储位置中的两个地址的指示来保持精确的依赖性检查在堆栈缓存内。

5. 发明授权

US5991869A Superscalar microprocessor including a high speed instruction alignment unit 失效
标题翻译：超标量微处理器包括高速指令对齐单元
公开(公告)号：US5991869A
公开(公告)日：1999-11-23
申请号：US968907
申请日：1997-11-06
申请人： Thang Tran , David B. Witt , William M. Johnson
发明人： Thang Tran , David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A superscalar microprocessor having an instruction alignment unit, an instruction cache, a plurality of decode units and a predecode unit is provided. The instruction alignment unit transfers a fixed number of instructions from the instruction cache to each of the plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by the predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to the plurality of decode units.
摘要翻译：提供了具有指令对准单元，指令高速缓存，多个解码单元和预解码单元的超标量微处理器。指令对准单元将固定数量的指令从指令高速缓存传送到多个解码单元中的每一个。根据由预解码单元生成的预解码标签，从指定的字节数中选择指令。预解码标签包括开始字节位，指示字节数量中的哪个字节是指令的第一个字节。指令对准单元独立地扫描多组指令字节，为多个发行位置中的每一个选择开始字节和多个连续字节。最初，指令对准单元为多组指令中的每一组选择一组发行位置。然后，指令对准单元移动并合并独立产生的发行位置，以产生用于传送到多个解码单元的发行位置的最终集合。

6. 发明授权

US5891476A Tastemasked pharmaceutical system 失效
标题翻译：过滤药物系统
公开(公告)号：US5891476A
公开(公告)日：1999-04-06
申请号：US995466
申请日：1997-12-22
申请人： Joe P. Reo , William M. Johnson
发明人： Joe P. Reo , William M. Johnson
IPC分类号： A61K9/00 , A61K9/16 , A61K9/42 , A61K9/50 , A61K9/107 , A61K9/56
CPC分类号： A61K9/5015 , A61K9/0056 , A61K9/1617
摘要： The present invention provides a drug delivery system containing a pharmaceutically active core and a coating of the core. The coating is comprised of a an emulsifier and a wax. The coating provides rapid dissolution and enhanced long-term stability for the pharmaceutically active ingredient.
摘要翻译：本发明提供了含有药学活性核心和核心涂层的药物递送系统。涂层由乳化剂和蜡组成。该涂层提供药物活性成分的快速溶解和增强的长期稳定性。

7. 发明授权

US5867682A High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations 失效
标题翻译：高性能超标量微处理器，包括用于将CISC指令转换为RISC操作的电路
公开(公告)号：US5867682A
公开(公告)日：1999-02-02
申请号：US599696
申请日：1996-02-09
申请人： David B. Witt , William M. Johnson
发明人： David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
摘要翻译：提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。指令以推测顺序从解码器发出，发出无序，完成无序。指令从重新排序缓冲区中重新排序到寄存器文件。微处理器的功能单元期望地容纳显示多个数据宽度的操作数。通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

8. 发明授权

US5848287A Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches 失效
标题翻译：超标量微处理器包括重新排序缓冲器，其检测对一对高速缓存的访问之间的依赖性
公开(公告)号：US5848287A
公开(公告)日：1998-12-08
申请号：US603804
申请日：1996-02-20
申请人： Thang M. Tran , David B. Witt , William M. Johnson
发明人： Thang M. Tran , David B. Witt , William M. Johnson
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is provided within the microprocessor. The dependency checking structure compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage. The comparator circuits used to perform the comparison are configured to compare a field of address bits instead of the entire address, reducing the size while still maintaining accurate dependency checking by qualifying the resulting comparison signals with an indication that both addresses hit in the same storage location within the stack cache.
摘要翻译：提供了一种超标量微处理器，其保持从指令处理流水线的不同阶段访问的一对缓存之间的一致性。在微处理器内提供依赖检查结构。依赖性检查结构将从指令处理流水线的执行阶段执行的存储器访问与从解码级执行的存储器访问进行比较。解码级对堆栈高速缓存执行存储器访问，而执行级通过间接寻址将其访问（通过间接寻址形成的地址）执行到堆栈高速缓存和数据高速缓存。如果由执行级执行的读取存储器访问取决于由解码级执行的写存储器访问，则读存储器访问被停止，直到写存储器访问完成。如果由解码级执行的读取存储器访问取决于由执行级执行的写入存储器访问，则刷新与读取的存储器访问和后续指令相关联的指令。在一对缓存之间保持数据一致性，同时允许从解码级执行堆栈相对访问。用于执行比较的比较器电路被配置为比较地址位的字段而不是整个地址，减小大小，同时仍然通过将所得到的比较信号限定在相同存储位置中的两个地址的指示来保持精确的依赖性检查在堆栈缓存内。

9. 发明授权

US5845101A Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache 失效
标题翻译：用于在将指令放置在指令高速缓存之前存储指令的预取缓冲器
公开(公告)号：US5845101A
公开(公告)日：1998-12-01
申请号：US855099
申请日：1997-05-13
申请人： William M. Johnson , Thang M. Tran , Matt T. Gavin , Mike Pedneau
发明人： William M. Johnson , Thang M. Tran , Matt T. Gavin , Mike Pedneau
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A microprocessor is configured to speculatively fetch cache lines of instruction bytes prior to actually detecting a cache miss for the cache lines of instruction bytes. The bytes transferred from an external main memory subsystem are stored into one of several prefetch buffers. Subsequently, instruction fetches may be detected which hit the prefetch buffers. Furthermore, predecode data may be generated for the instruction bytes stored in the prefetch buffers. When a fetch hit in the prefetch buffers is detected, predecode data may be available for the instructions being fetched. The prefetch buffers may each comprise an address prefetch buffer included within an external interface unit and an instruction data prefetch buffer included within a prefetch/predecode unit. The external interface unit maintains the addresses of cache lines assigned to the prefetch buffers in the address prefetch buffers. Both the linear address and the physical address of each cache line is maintained. The prefetch/predecode unit receives instruction bytes directly from the external interface and stores the instruction bytes in the corresponding instruction data prefetch buffer.
摘要翻译：微处理器被配置为在实际检测到指令字节的高速缓存行的高速缓存未命中之前推测性地提取指令字节的高速缓存行。从外部主存储器子系统传送的字节存储在几个预取缓冲器之一中。随后，可以检测到命中提取缓冲器的指令提取。此外，可以为存储在预取缓冲器中的指令字节产生预解码数据。当检测到预取缓冲器中的提取命中时，预解码数据可能对于正在获取的指令可用。预取缓冲器可以各自包括包含在外部接口单元内的地址预取缓冲器和包含在预取/预解码单元内的指令数据预取缓冲器。外部接口单元维护分配给地址预取缓冲器中的预取缓冲器的高速缓存线的地址。保持每个高速缓存行的线性地址和物理地址。预取/预解码单元直接从外部接口接收指令字节，并将指令字节存储在相应的指令数据预取缓冲器中。

10. 发明授权

US5787266A Apparatus and method for accessing special registers without serialization 失效
标题翻译：用于访问特殊寄存器而不进行序列化的设备和方法
公开(公告)号：US5787266A
公开(公告)日：1998-07-28
申请号：US603805
申请日：1996-02-20
申请人： William M. Johnson , Thang M. Tran , Rupaka Mahalingaiah
发明人： William M. Johnson , Thang M. Tran , Rupaka Mahalingaiah
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30167 , G06F9/30101 , G06F9/30152 , G06F9/30163 , G06F9/382 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are dispatched, and stores an indication of the write in a special register dependency block. Instructions subsequent to the special register write instruction are examined for both explicit and implicit dependencies upon the special register write. If a dependency is detected with respect to a particular instruction, the instruction is dispatched to a reservation station along with an indication of the dependency. Instructions subsequent to the special register write instruction which are not dependent upon the special register are dispatched without an indication of special register dependency. Instructions without dependencies may speculatively execute prior to instructions with dependencies, or even prior to the special register write instruction. In one particular embodiment employing the x86 microprocessor architecture, the microprocessor detects updates to the DS, ES, FS, and GS segment registers (i.e. the data segment registers). Updates to other segment registers are serialized.
摘要翻译：提供了一种使用不进行串行化来执行特殊寄存器写入的装置的微处理器。当调度指令时，该设备检测特殊寄存器写指令，并将写入的指示存储在特殊寄存器依赖块中。在特殊寄存器写入指令之后的指令将针对特殊寄存器写入时的显式和隐式依赖性进行检查。如果相对于特定指令检测到依赖关系，则将该指令与依赖性的指示一起发送到保留站。在不依赖于特殊寄存器的特殊寄存器写入指令之后的指令被调度，而不指示特殊寄存器依赖性。没有依赖性的指令可以在具有依赖性的指令之前，甚至在特殊寄存器写指令之前推测执行。在采用x86微处理器架构的一个特定实施例中，微处理器检测对DS，ES，FS和GS段寄存器（即，数据段寄存器）的更新。其他段寄存器的更新被序列化。

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