专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4777588A General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance 失效
标题翻译：通用寄存器文件优化用于进行内部寄存器分配，过程调用和多任务性能
公开(公告)号：US4777588A
公开(公告)日：1988-10-11
申请号：US771311
申请日：1985-08-30
申请人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
发明人： Brian W. Case , Rod G. Fleck , William M. Johnson , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/30 , G06F9/34 , G06F9/40 , G06F9/46 , G06F9/48 , G06F12/14
CPC分类号： G06F9/468 , G06F12/1458 , G06F9/4425 , G06F9/462
摘要： A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.
摘要翻译：公开了一种适用于精简指令集计算机（RISC）的指令处理器所使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。寄存器文件通过动态地提供两个过程可访问的重叠寄存器来促进过程之间的参数传递。每个过程也有一组分配给它的“本地”寄存器，不能从其他过程访问。寄存器文件被分成多个块，并且保护寄存器存储一个单词，其禁止特定过程或任务访问某些块。以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，从而保持每个任务的完整性，而不是在其他任务中发生不希望的变化。

2. 发明授权

US4777587A System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses 失效
标题翻译：在具有相对，绝对，间接和陷阱地址的管道中处理单周期分支指令的系统
公开(公告)号：US4777587A
公开(公告)日：1988-10-11
申请号：US771327
申请日：1985-08-30
申请人： Brian W. Case , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
发明人： Brian W. Case , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/32 , G06F9/38 , G06F9/48 , G06F9/00 , G06F9/42
CPC分类号： G06F9/30058 , G06F9/3842
摘要： An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.
摘要翻译：适用于简化指令集计算机的指令处理器采用在单个处理器周期中执行条件分支的指令流水线。处理器将分支条件视为常规指令操作数，而不是单独条件代码寄存器中的特殊情况。条件位和分支目标地址确定要获取哪个指令，分支在执行下一条指令之前不起作用。以这种方式，不需要在流水线中物理地跟随分支指令的指令的替换，并且分支发生在分配给它的流水线的单个周期内。一个简单的电路实现这种延迟分支方法。结合处理器的计算机容易地执行用于子程序，中断和陷阱的调用的特殊处理技术。

3. 发明授权

US4734852A Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor 失效
标题翻译：在精简指令集处理器上执行指令并行执行存储数据引用的机制
公开(公告)号：US4734852A
公开(公告)日：1988-03-29
申请号：US771435
申请日：1985-08-30
申请人： William M. Johnson , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
发明人： William M. Johnson , Rod G. Fleck , Cheng-Gang Kong , Ole Moller
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3834
摘要： A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.
摘要翻译：实现与指令执行并行执行存储数据引用的机制的简单架构。该架构特别适用于简化指令集计算机（RISC），并采用通道地址寄存器来存储主存储器加载或存储地址，临时存储来自存储操作的数据的通道数据寄存器和通道控制寄存器，在加载操作的情况下，包含控制信息，包括在文件中加载的寄存器的编号。该数字用于检测要加载的数据的指令依赖性。如果负载所需的数据尚不可用，则逻辑电路将暂停进一步的指令处理。数据输入寄存器用于存储负载数据，直到指令执行周期可用于将其写回寄存器文件。逻辑电路在写入之前检测数据的存储，以便有效地替换寄存器文件位置。在页面故障期间，保存通道地址，通道数据和通道控制寄存器的内容，以允许页面故障恢复。

4. 发明授权

US4926323A Streamlined instruction processor 失效
标题翻译：精简指令处理器
公开(公告)号：US4926323A
公开(公告)日：1990-05-15
申请号：US163917
申请日：1988-03-03
申请人： Gigy Baror , Brian W. Case , Rod G. Fleck , Philip M. Freidin , Smeeta Gupta , William M. Johnson , Cheng-Gang Kong , Ole H. Moller , Timothy A. Olson , David I. Sorensen
发明人： Gigy Baror , Brian W. Case , Rod G. Fleck , Philip M. Freidin , Smeeta Gupta , William M. Johnson , Cheng-Gang Kong , Ole H. Moller , Timothy A. Olson , David I. Sorensen
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3867
摘要： A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles. The execution unit includes a storage facility, coupled to the data interface, for storing data in a file of data locations identified by file addresses. The storage facility includes at least two read ports and one write port operable in response to file addresses. An addressing unit coupled to receive the instructions from the instruction register, supplies the file addresses to the read ports and the write port under program control. In addition, the addressing unit is operable in response to a stack pointer providing dynamic allocation of the file of data locations to processes within the program.A memory management unit is coupled to the data interface. The memory management unit includes an address interface adapted for connection to the data memory and the instruction memory for supplying instruction addresses to the instruction memory and data addresses to the data memory, in a simple single access mode, a pipeline mode and a burst mode.
摘要翻译：精简指令处理器响应于由流水线循环中的预先指定组成的程序来处理数据。处理器包括指令提取单元，其包括适于连接到指令存储器并用于从指令存储器取出指令的指令接口。指令提取单元包括指令预取缓冲器，其耦合到指令接口，用于缓冲提供给指令接口的指令序列。分支目标高速缓冲存储器与预取缓冲器耦合，用于存储从指令存储器中的对应的一组位置检索的具有顺序指令地址的指令集。每个这样的集合中的第一条指令是程序中的分支目标指令。此外，包括适于连接到数据存储器的数据接口的执行单元在流水线循环中执行指令。执行单元包括耦合到数据接口的存储设备，用于将数据存储在由文件地址标识的数据位置的文件中。存储设备包括至少两个读端口和一个可响应文件地址操作的写端口。耦合以从指令寄存器接收指令的寻址单元，在程序控制下将文件地址提供给读端口和写端口。此外，寻址单元响应于堆栈指针提供动态分配数据位置文件到程序内的进程而可操作。存储器管理单元耦合到数据接口。存储器管理单元包括适于连接到数据存储器的地址接口和用于以简单的单次访问模式，流水线模式和突发模式向指令存储器提供指令地址和数据存储器的指令存储器。

5. 发明申请

US20120194248A1 NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA STROBE 有权
标题翻译：非线性常规延迟系统和延迟数据结构的方法
公开(公告)号：US20120194248A1
公开(公告)日：2012-08-02
申请号：US13016472
申请日：2011-01-28
申请人： Terence J. Magee , Christopher D. Paulson , Cheng-Gang Kong
发明人： Terence J. Magee , Christopher D. Paulson , Cheng-Gang Kong
IPC分类号： H03H11/26 , G01R29/00 , G06F19/00 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222
摘要： A non-linear common coarse delay system and method for delaying a data strobe in order to preserve fine delay accuracy and compensate PVT (Process, Voltage, and Temperature) variation effects. A common coarse delay and a fine delay can be initialized to a quarter-cycle delay for shifting a read output DQS (Data Queue Strobe) associated with a memory device in order to sample a read output DQ (Data Queue) within a physical layer. The fine delay can be programmed from minimum to maximum delay with fixed linear increments at each delay step in order to determine the resolution and accuracy of the delay. An optimum delay size of both the coarse and the fine delay can be determined based on an application slowest frequency of operation. A spare coarse delay and a functional coarse delay can be trained in association with a spare fine delay and the functional fine delay can be updated in order to monitor the process, voltage, and temperature variation effects.
摘要翻译：用于延迟数据选通的非线性公共粗延迟系统和方法，以便保持精细的延迟精度并补偿PVT（过程，电压和温度）变化的影响。普通粗延迟和精细延迟可以初始化为四分之一周期的延迟，用于移位与存储器件相关联的读输出DQS（数据队列选通），以便对物理层内的读输出DQ（数据队列）进行采样。在每个延迟步骤中，精细延迟可以从最小到最大延迟编程为固定的线性增量，以便确定延迟的分辨率和精度。基于应用最慢的操作频率，可以确定粗略和精细延迟的最佳延迟大小。可以与备用精细延迟相关联地训练备用粗延迟和功能粗延迟，并且可以更新功能精细延迟以便监视过程，电压和温度变化效应。

6. 发明授权

US07839716B2 Apparatus and systems for VT invariant DDR3 SDRAM write leveling 有权
标题翻译：用于VT不变式DDR3 SDRAM写入调平的装置和系统
公开(公告)号：US07839716B2
公开(公告)日：2010-11-23
申请号：US12339232
申请日：2008-12-19
申请人： Cheng-Gang Kong , Thomas Hughes
发明人： Cheng-Gang Kong , Thomas Hughes
IPC分类号： G11C8/16
CPC分类号： G11C8/18 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C8/12
摘要： Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.
摘要翻译：用于改进DDR3存储器子系统中的PVT不变快速级别切换的装置和系统。时钟偏移控制电路设置在存储器控制器和DDR3 SDRAM存储器子系统之间，以调整DDR3时钟信号与数据相关信号（例如DQ和/或DQS）之间的偏差。初始写入调平过程确定正确的偏移，并对偏斜调整电路中的寄存器文件进行编程。寄存器文件包括DDR3存储器中多个级别中的每一个的寄存器。每个寄存器中的值用于控制数据相关信号的对准选择，以与1×DDR3时钟信号的多个相移版本中的一个对准。相移时钟信号由时钟分频器电路从2×DDR时钟信号产生，并使用近似1×DDR3时钟周期的单个固定延迟线。

7. 发明申请

US20080068911A1 System and method for providing swap path voltage and temperature compensation 失效
标题翻译：提供交换路径电压和温度补偿的系统和方法
公开(公告)号：US20080068911A1
公开(公告)日：2008-03-20
申请号：US11523139
申请日：2006-09-19
申请人： Thomas Hughes , Cheng-Gang Kong
发明人： Thomas Hughes , Cheng-Gang Kong
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2254
摘要： The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.
摘要翻译：本发明是数据路径电压和温度补偿的方法。该方法包括配置脱机数据路径以匹配在线数据路径。该方法还包括补偿离线数据路径的电压和温度变化。该方法还包括将离线数据路径与在线数据路径进行交换。此外，交换自动发生而不中断沿数据路径的数据流。

8. 发明申请

US20060288175A1 Feedback programmable data strobe enable architecture for DDR memory applications 有权
标题翻译：用于DDR存储器应用的反馈可编程数据选通使能架构
公开(公告)号：US20060288175A1
公开(公告)日：2006-12-21
申请号：US11154401
申请日：2005-06-16
申请人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
发明人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为通过多个输入/输出线读取和写入数据。第二电路可以包括多个部分。每个部分可以被配置为向负载输出线呈现控制信号，并通过负载输入线接收控制信号的反馈。每个部分的负载输入线和负载输出线可以连接到被配置为匹配连接到多个输入/输出线中的每一个的相应存储器负载的负载电路。

9. 发明申请

US20060132210A1 Wide-range programmable delay line 有权
公开(公告)号：US20060132210A1
公开(公告)日：2006-06-22
申请号：US11021361
申请日：2004-12-22
申请人： Cheng-Gang Kong , Victor Suen
发明人： Cheng-Gang Kong , Victor Suen
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00071
摘要： An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

10. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式