专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07475223B2 Fetch-side instruction dispatch group formation 失效
标题翻译：抓取指令分派组
公开(公告)号：US07475223B2
公开(公告)日：2009-01-06
申请号：US11050367
申请日：2005-02-03
申请人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/00
CPC分类号： G06F9/3853 , G06F9/3802 , G06F9/382 , G06F9/3851
摘要： An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in the instruction cache.
摘要翻译：用于分组指令的改进的方法，装置和计算机指令。接收一组指令以放置在数据处理系统中的指令高速缓存中。指令集中的指令在被放置在指令高速缓存中的指令集之前被分组成指令的分派组合。

2. 发明授权

US07487334B2 Branch encoding before instruction cache write 有权
标题翻译：指令缓存写入前的分支编码
公开(公告)号：US07487334B2
公开(公告)日：2009-02-03
申请号：US11050350
申请日：2005-02-03
申请人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/34
CPC分类号： G06F9/322 , G06F9/382
摘要： Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.
摘要翻译：用于确定数据处理系统中分支目标的方法，系统和计算机程序产品。一种用于确定数据处理系统中的分支的目标的方法包括在将分支写入级别1（L1）高速缓存之前执行与确定分支的目标有关的至少一个预计算，以提供预解码分支，然后将预解码的分支写入L1高速缓存。通过在将分支写入L1高速缓存之前预先计算与分支目标相关的事项，例如通过将相关分支重新编码为绝对分支，可以实现分支重定向延迟的减少，从而提供了显着的改进整体处理器性能。

3. 发明授权

US07269715B2 Instruction grouping history on fetch-side dispatch group formation 失效
标题翻译：指令分组历史在抓取方调度组的形成
公开(公告)号：US07269715B2
公开(公告)日：2007-09-11
申请号：US11050344
申请日：2005-02-03
申请人： Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3802 , G06F9/382
摘要： An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a prior set of instructions received in the instruction cache including using a history data structure, wherein the history data structure contains data regarding instructions in the prior set of instructions. Any instructions are grouped into the group with the instruction in response to a determination that the any instructions are part of the group. Instructions in the group units are dispatched to execution using the history data structure, wherein invalid instruction dispatch groupings are avoided.
摘要翻译：一种改进的方法，装置和计算机指令，用于对在相同大小的集合中处理的指令进行分组。在指令高速缓存中接收当前的一组指令用于调度。确定当前指令集中的任何指令是否包括包括使用历史数据结构在指令高速缓存中接收的先前指令集的组的一部分，其中历史数据结构包含关于先前的指令的数据一套说明响应于确定任何指令是组的一部分，任何指令被分组到具有指令的组中。使用历史数据结构将分组单元中的指令调度到执行，其中避免了无效指令分派分组。

4. 发明授权

US07237094B2 Instruction group formation and mechanism for SMT dispatch 失效
标题翻译： SMT派遣指导小组组织和机制
公开(公告)号：US07237094B2
公开(公告)日：2007-06-26
申请号：US10965143
申请日：2004-10-14
申请人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
发明人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/382 , G06F9/3851 , G06F9/3885
摘要： A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.
摘要翻译：通过将资源字段与相应的程序指令相关联来处理计算机处理器中的指令的更有效的方法，其中资源字段指示需要哪个处理器硬件资源来执行程序指令，计算用于合并两个或多个程序指令的资源需求并且基于所计算的资源需求来确定用于同时执行所合并的程序指令的资源可用性。指示所需资源的资源矢量可以被编码到资源字段中，并且在稍后阶段解码资源字段以导出资源向量。资源字段可以存储在与相应的程序指令相关联的指令高速缓存中。处理器可以以同时多线程模式操作，其中不同的程序指令是不同硬件线程的一部分。当资源可用性等于或超过一组指令的资源需求时，可以将这些指令同时发送到硬件资源。可以在程序指令之一中插入起始位以定义指令组。硬件资源可以特别地是诸如定点单元，加载/存储单元，浮点单元或分支处理单元之类的执行单元。

5. 发明授权

US5805849A Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions 失效
标题翻译：用于使用唯一标识符来维护执行指令之间的年龄关系的数据处理系统和方法
公开(公告)号：US5805849A
公开(公告)日：1998-09-08
申请号：US829592
申请日：1997-03-31
申请人： Paul Joseph Jordan , Brian R. Konigsburg , Hung Qui Le , Steven Wayne White
发明人： Paul Joseph Jordan , Brian R. Konigsburg , Hung Qui Le , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3857
摘要： A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor. The global signal preconditions portions of the two identifiers being compared. Subsequently, a result of this conditioning is concatenated with a remaining portion of a selected identifier. The modification of the upper bits of the identifier maintains a relative age position for the identifiers and their associated instructions in the pipelined processor.
摘要翻译：数据处理器为每个指令分配唯一的标识符。由于存在有限数量的唯一标识符，所以在数据处理系统内的程序执行期间重新使用标识符。为了保持在流水线处理器中执行的指令之间的年龄关系，开发了一种方法，以确保重复使用的标识符被正确地指定为年龄小于较大的，较大的数量。为了解决这个问题，假定分配给每个指令的标识符具有N位，因此，有2N个标识符被分配给程序中的指令。 2N个标识符分成2m个银行。除了为每个指令分配标识符之外，流水线处理器内的标识符分配逻辑电路提供一个全局信号，其指示哪个存储体是最小的存储体，其中标识符从其被分配给流水线处理器的剩余部分。两个标识符的全局信号前提条件部分被比较。随后，这种调理的结果与所选标识符的剩余部分连接。标识符的高位的修改保持流水线处理器中的标识符及其相关联的指令的相对年龄位置。

6. 发明授权

US06286094B1 Method and system for optimizing the fetching of dispatch groups in a superscalar processor 有权
标题翻译：用于优化超标量处理器中调度组的获取的方法和系统
公开(公告)号：US06286094B1
公开(公告)日：2001-09-04
申请号：US09263663
申请日：1999-03-05
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.
摘要翻译：公开了一种用于确定处理系统中是否需要调度槽的方法和系统。所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

7. 发明授权

US08347068B2 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor 有权
标题翻译：多模式寄存器重命名机制，通过在同时多线程微处理器中的顺序和无序指令处理之间切换时，通过从寄存器重命名缓冲器切换物理寄存器来增加逻辑寄存器
公开(公告)号：US08347068B2
公开(公告)日：2013-01-01
申请号：US11696363
申请日：2007-04-04
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30145 , G06F9/30189 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.
摘要翻译：多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

8. 发明授权

US07904661B2 Data stream prefetching in a microprocessor 失效
标题翻译：数据流在微处理器中预取
公开(公告)号：US07904661B2
公开(公告)日：2011-03-08
申请号：US11953637
申请日：2007-12-10
申请人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
发明人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.
摘要翻译：在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。数据预取请求被分配与数据流以反映确定的数据流的深度。分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。由处理器执行的指令中的预取控制位控制预取硬件配置。

9. 发明授权

US07827443B2 Processor instruction retry recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US07827443B2
公开(公告)日：2010-11-02
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

10. 发明授权

US07650486B2 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions 有权
标题翻译：动态重新计算依赖指令转向问题队列中的资源向量
公开(公告)号：US07650486B2
公开(公告)日：2010-01-19
申请号：US12013572
申请日：2008-01-14
申请人： Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto , Raymond Cheung Yeung
发明人： Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式