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1. 发明授权

US07487334B2 Branch encoding before instruction cache write 有权
标题翻译：指令缓存写入前的分支编码
公开(公告)号：US07487334B2
公开(公告)日：2009-02-03
申请号：US11050350
申请日：2005-02-03
申请人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/34
CPC分类号： G06F9/322 , G06F9/382
摘要： Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.
摘要翻译：用于确定数据处理系统中分支目标的方法，系统和计算机程序产品。一种用于确定数据处理系统中的分支的目标的方法包括在将分支写入级别1（L1）高速缓存之前执行与确定分支的目标有关的至少一个预计算，以提供预解码分支，然后将预解码的分支写入L1高速缓存。通过在将分支写入L1高速缓存之前预先计算与分支目标相关的事项，例如通过将相关分支重新编码为绝对分支，可以实现分支重定向延迟的减少，从而提供了显着的改进整体处理器性能。

2. 发明授权

US07475223B2 Fetch-side instruction dispatch group formation 失效
标题翻译：抓取指令分派组
公开(公告)号：US07475223B2
公开(公告)日：2009-01-06
申请号：US11050367
申请日：2005-02-03
申请人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Brian R. Konigsburg , Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/00
CPC分类号： G06F9/3853 , G06F9/3802 , G06F9/382 , G06F9/3851
摘要： An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in the instruction cache.
摘要翻译：用于分组指令的改进的方法，装置和计算机指令。接收一组指令以放置在数据处理系统中的指令高速缓存中。指令集中的指令在被放置在指令高速缓存中的指令集之前被分组成指令的分派组合。

3. 发明授权

US07269715B2 Instruction grouping history on fetch-side dispatch group formation 失效
标题翻译：指令分组历史在抓取方调度组的形成
公开(公告)号：US07269715B2
公开(公告)日：2007-09-11
申请号：US11050344
申请日：2005-02-03
申请人： Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
发明人： Hung Qui Le , David Stephen Levitan , John Wesley Ward, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3802 , G06F9/382
摘要： An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a prior set of instructions received in the instruction cache including using a history data structure, wherein the history data structure contains data regarding instructions in the prior set of instructions. Any instructions are grouped into the group with the instruction in response to a determination that the any instructions are part of the group. Instructions in the group units are dispatched to execution using the history data structure, wherein invalid instruction dispatch groupings are avoided.
摘要翻译：一种改进的方法，装置和计算机指令，用于对在相同大小的集合中处理的指令进行分组。在指令高速缓存中接收当前的一组指令用于调度。确定当前指令集中的任何指令是否包括包括使用历史数据结构在指令高速缓存中接收的先前指令集的组的一部分，其中历史数据结构包含关于先前的指令的数据一套说明响应于确定任何指令是组的一部分，任何指令被分组到具有指令的组中。使用历史数据结构将分组单元中的指令调度到执行，其中避免了无效指令分派分组。

4. 发明申请

US20080276080A1 METHODS FOR STORING BRANCH INFORMATION IN AN ADDRESS TABLE OF A PROCESSOR 有权
标题翻译：在处理器的地址表中存储分支信息的方法
公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

5. 发明授权

US06279105B1 Pipelined two-cycle branch target address cache 失效
标题翻译：流水线两循环分支目标地址缓存
公开(公告)号：US06279105B1
公开(公告)日：2001-08-21
申请号：US09173039
申请日：1998-10-15
申请人： Brian R. Konigsburg , David Stephen Levitan
发明人： Brian R. Konigsburg , David Stephen Levitan
IPC分类号： G06F1300
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3861
摘要： In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.
摘要翻译：在分支指令目标地址高速缓存中，与获取的指令块相关联的条目包括驻留在下一个顺序指令块中的分支指令的目标地址。条目将包括与分支指令相关联的顺序地址以及是否采取目标地址的预测。

6. 发明授权

US07984280B2 Storing branch information in an address table of a processor 有权
标题翻译：将分支信息存储在处理器的地址表中
公开(公告)号：US07984280B2
公开(公告)日：2011-07-19
申请号：US12171370
申请日：2008-07-11
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

7. 发明授权

US08943301B2 Storing branch information in an address table of a processor 有权
标题翻译：将分支信息存储在处理器的地址表中
公开(公告)号：US08943301B2
公开(公告)日：2015-01-27
申请号：US13101650
申请日：2011-05-05
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

8. 发明授权

US06385719B1 Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中同步并行管线的方法和装置
公开(公告)号：US06385719B1
公开(公告)日：2002-05-07
申请号：US09345719
申请日：1999-06-30
申请人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
发明人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.
摘要翻译：传送标签由指令提取单元生成，并在指令流水线中传送给解码单元，每个指令组由读取器在分支预测期间取出。为分支流水线提取的组中的单独指令被分配用于匹配在刷新任何较新指令的请求上的传送标签的级联版本（组标签与指令通道连接）。解码流水线中的所有潜在指令或内部操作锁存器必须执行匹配，并且如果遇到匹配，将清除与较新指令相关联的所有有效位或匹配上游的内部操作。表示在分支管线中要处理的下一条指令的传送标签被传递到指令调度单元。指令调度单元查询分支流水线以将其传输标签与分支流水线中的指令的传输标签进行比较。如果转移标签与分支指令标签匹配，则指令解码单元停止，直到处理分支指令为止，为并行管线提供同步方法。

9. 发明申请

US20110213951A1 Storing Branch Information in an Address Table of a Processor 审中-公开
标题翻译：将分支信息存储在处理器的地址表中
公开(公告)号：US20110213951A1
公开(公告)日：2011-09-01
申请号：US13101650
申请日：2011-05-05
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

10. 发明授权

US07426631B2 Methods and systems for storing branch information in an address table of a processor 失效
标题翻译：用于将分支信息存储在处理器的地址表中的方法和系统
公开(公告)号：US07426631B2
公开(公告)日：2008-09-16
申请号：US11049014
申请日：2005-02-02
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F9/40 , G06F9/355
CPC分类号： G06F9/3806
摘要： Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法和系统。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

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