会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Method for attaching a fluid container to a fluid ejector in a fluid ejection device
    • 将流体容器附接到流体喷射装置中的流体喷射器的方法
    • US20050168508A1
    • 2005-08-04
    • US10766008
    • 2004-01-29
    • Brian HiltonEric MerzTakatoshi TsuchiyaHiroki Murakami
    • Brian HiltonEric MerzTakatoshi TsuchiyaHiroki Murakami
    • B41J2/16B41J2/175B41J29/38
    • B41J2/17513B41J2/17509Y10T156/1043
    • A method for joining fluid containers and fluid ejectors in a fluid ejecting device are provided. The fluid container includes one or more heat stakes and a substrate includes one or more apertures for receiving the heat stakes and one or more three-dimensional features in the vicinity of the one or more apertures. The fluid ejector and optionally an elastic member are interposed between the fluid container and the substrate. Thermal energy is applied to the one or more heat stakes so that the one or more heat stakes soften to occupy the apertures and three-dimensional features of the substrate and pressure is applied to maintain contact between the fluid container, elastic member, fluid ejector and substrate. The present invention is also directed to substrate including one or more apertures for receiving heat stakes and one or more three-dimensional features in the vicinity of the one or more apertures.
    • 提供了一种在流体喷射装置中连接流体容器和流体喷射器的方法。 流体容器包括一个或多个热桩,并且衬底包括用于接收热桩的一个或多个孔和一个或多个孔附近的一个或多个三维特征。 流体喷射器和可选地弹性构件插入在流体容器和基底之间。 将热能施加到一个或多个热桩上,使得一个或多个热桩软化以占据孔,并且施加衬底的三维特征并施加压力以保持流体容器,弹性构件,流体喷射器和 基质。 本发明还涉及包括用于接收热桩的一个或多个孔和一个或多个孔附近的一个或多个三维特征的衬底。
    • 2. 发明授权
    • Method for attaching a fluid container to a fluid ejector in a fluid ejection device
    • 将流体容器附接到流体喷射装置中的流体喷射器的方法
    • US07294223B2
    • 2007-11-13
    • US10766008
    • 2004-01-29
    • Brian S. HiltonEric A. MerzTakatoshi TsuchiyaHiroki Murakami
    • Brian S. HiltonEric A. MerzTakatoshi TsuchiyaHiroki Murakami
    • B29C65/00
    • B41J2/17513B41J2/17509Y10T156/1043
    • A method for joining fluid containers and fluid ejectors in a fluid ejecting device are provided. The fluid container includes one or more heat stakes and a substrate includes one or more apertures for receiving the heat stakes and one or more three-dimensional features in the vicinity of the one or more apertures. The fluid ejector and optionally an elastic member are interposed between the fluid container and the substrate. Thermal energy is applied to the one or more heat stakes so that the one or more heat stakes soften to occupy the apertures and three-dimensional features of the substrate and pressure is applied to maintain contact between the fluid container, elastic member, fluid ejector and substrate. The present invention is also directed to substrate including one or more apertures for receiving heat stakes and one or more three-dimensional features in the vicinity of the one or more apertures.
    • 提供了一种在流体喷射装置中连接流体容器和流体喷射器的方法。 流体容器包括一个或多个热桩,并且衬底包括用于接收热桩的一个或多个孔和一个或多个孔附近的一个或多个三维特征。 流体喷射器和可选地弹性构件插入在流体容器和基底之间。 将热能施加到一个或多个热桩上,使得一个或多个热桩软化以占据孔,并且施加衬底的三维特征并施加压力以保持流体容器,弹性构件,流体喷射器和 基质。 本发明还涉及包括用于接收热桩的一个或多个孔和在一个或多个孔附近的一个或多个三维特征的衬底。
    • 3. 发明授权
    • Semiconductor memory device with a clock circuit for reducing power consumption in a standby state
    • 具有用于在待机状态下降低功耗的时钟电路的半导体存储器件
    • US09112488B2
    • 2015-08-18
    • US13303153
    • 2011-11-23
    • Hiroki Murakami
    • Hiroki Murakami
    • G11C7/10G11C7/22G11C5/14H03K19/00G11C16/20G11C16/30
    • H03K19/0016G11C5/147G11C5/148G11C7/1057G11C7/1084G11C7/225G11C16/20G11C16/30G11C2207/2227
    • A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.
    • 提供一种包括能够减少在待机状态期间发生的漏电流的逻辑电路的半导体器件。 半导体器件包括用于提供第一操作电压的电源部分或小于第一操作电压的第二操作电压; 用于从电源部分接收第一或第二操作电压的P型低阈值晶体管Tp; 以及连接在晶体管Tp和基极之间的N型晶体管Tn。 晶体管Tp,Tn构成逻辑电路。 电源部在使能状态下将第一工作电压提供给晶体管Tp的源极,将第二工作电压供给到待机状态。 第二操作电压被设置为使得每个晶体管Tp,Tn的栅极和源极之间的电压幅度大于晶体管Tp,Tn的阈值。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120287712A1
    • 2012-11-15
    • US13303153
    • 2011-11-23
    • Hiroki Murakami
    • Hiroki Murakami
    • G11C16/04H03K19/00H03K19/20G11C5/06H03K19/096
    • H03K19/0016G11C5/147G11C5/148G11C7/1057G11C7/1084G11C7/225G11C16/20G11C16/30G11C2207/2227
    • A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.
    • 提供一种包括能够减少在待机状态期间发生的漏电流的逻辑电路的半导体器件。 半导体器件包括用于提供第一操作电压的电源部分或小于第一操作电压的第二操作电压; 用于从电源部分接收第一或第二操作电压的P型低阈值晶体管Tp; 以及连接在晶体管Tp和基极之间的N型晶体管Tn。 晶体管Tp,Tn构成逻辑电路。 电源部在使能状态下将第一工作电压提供给晶体管Tp的源极,将第二工作电压供给到待机状态。 第二操作电压被设置为使得每个晶体管Tp,Tn的栅极和源极之间的电压幅度大于晶体管Tp,Tn的阈值。