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1. 发明申请

US20120303859A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING 有权
标题翻译：实现存储适配器性能优化与更新FOOTPRINT MIRRORING
公开(公告)号：US20120303859A1
公开(公告)日：2012-11-29
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其中，具有奇偶校验更新占用面积的双重适配器之间的镜像，最小化固件操作，以及提供了主题控制器电路所在的设计结构。第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储和非易失性随机存取存储器（NVRAM）。一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。

2. 发明申请

US20120303909A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE 失效
标题翻译：使用增强硬件和软件界面实现存储适配器性能优化
公开(公告)号：US20120303909A1
公开(公告)日：2012-11-29
申请号：US13114390
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00
CPC分类号： G06F3/0689 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F11/108 , G06F2211/1009
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.
摘要翻译：一种用于实现具有链接硬件操作的存储适配器性能优化的方法和控制器以及最小化硬件和固件交互的增强的硬件（HW）和固件（FW）接口，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和处理器。数据存储器被配置为存储多个控制块。全局工作队列包括选择性地布置在预定义链中以定义硬件操作序列的多个控制块。全局工作队列包括耦合到处理器和硬件引擎的队列输入以及耦合到硬件引擎的输出。控制块被布置在各自的引擎工作队列中，其被设计成控制各个硬件引擎的硬件操作，并且各个控制块被布置在事件队列中以向处理器提供完成结果。

3. 发明申请

US20120303886A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE CHAINS TO SELECT PERFORMANCE PATH 失效
标题翻译：实施存储适配器性能优化与硬件链选择性能路径
公开(公告)号：US20120303886A1
公开(公告)日：2012-11-29
申请号：US13114291
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
摘要翻译：一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。每个预定义链定义一系列操作。每个控制块被设计成控制多个硬件引擎之一的硬件操作。资源句柄结构被配置为基于系统的特定特征来选择预定义的链。每个预定义链被配置为实现特定的性能路径以最大化性能。

4. 发明申请

US20120304001A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH 失效
标题翻译：实施存储适配器性能优化与链接硬件操作和错误恢复固件路径
公开(公告)号：US20120304001A1
公开(公告)日：2012-11-29
申请号：US13114354
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20
CPC分类号： G06F11/0727 , G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F11/0793
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
摘要翻译：一种用于利用预定义的硬件操作链来实现存储适配器性能优化的方法和控制器，其被配置为最小化硬件和固件交互以及配置成选择用于错误恢复的固件序列的桥接代码，以响应于所述预定链中的所识别的错误来完成操作，并且设置有主体控制器电路所在的设计结构。所选择的预定义链被配置为实现特定的性能路径以最大化性能。响应于在预定义硬件链中的硬件操作期间识别的预定义错误，桥接代码被配置为选择用于其余操作的错误恢复完成的非性能路径固件序列。

5. 发明授权

US08886881B2 Implementing storage adapter performance optimization with parity update footprint mirroring 有权
标题翻译：实现具有奇偶校验更新占用空间镜像的存储适配器性能优化
公开(公告)号：US08886881B2
公开(公告)日：2014-11-11
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有奇偶校验更新占用面积的双重适配器最小化固件操作之间的镜像，以及提供主题控制器电路所在的设计结构。第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储和非易失性随机存取存储器（NVRAM）。一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。

6. 发明申请

US20120304198A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS 有权
标题翻译：实施存储适配器性能优化与链接硬件操作最小化硬件/固件交互
公开(公告)号：US20120304198A1
公开(公告)日：2012-11-29
申请号：US13114107
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F9/44
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有最小化硬件和固件交互的链接硬件操作，以及提供主题控制器电路驻留的设计结构。控制器包括多个硬件引擎; 和一个或多个处理器。事件队列被耦合到至少一个处理器通知多个预定义事件的处理器。控制块被设计成控制多个硬件引擎中的一个的操作，包括写入事件队列条目的硬件引擎。多个控制块被选择性地布置在预定义的链中以最小化硬件引擎将事件队列条目写入处理器。

7. 发明授权

US08495259B2 Implementing storage adapter performance optimization with hardware chains to select performance path 失效
标题翻译：使用硬件链实现存储适配器性能优化，以选择性能路径
公开(公告)号：US08495259B2
公开(公告)日：2013-07-23
申请号：US13114291
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
摘要翻译：一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。每个预定义链定义一系列操作。每个控制块被设计成控制多个硬件引擎之一的硬件操作。资源句柄结构被配置为基于系统的特定特征来选择预定义的链。每个预定义链被配置为实现特定的性能路径以最大化性能。

8. 发明申请

US20120297272A1 IMPLEMENTING ENHANCED IO DATA CONVERSION WITH PROTECTION INFORMATION MODEL INCLUDING PARITY FORMAT OF DATA INTEGRITY FIELDS 有权
标题翻译：实施具有保护信息模型的增强IO数据转换，包括数据完整性字段的特殊格式
公开(公告)号：US20120297272A1
公开(公告)日：2012-11-22
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F11/20
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

9. 发明授权

US08495469B2 Implementing enhanced IO data conversion with protection information model including parity format of data integrity fields 有权
标题翻译：使用包括数据完整性字段奇偶校验格式的保护信息模型来实现增强的IO数据转换
公开(公告)号：US08495469B2
公开(公告)日：2013-07-23
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F12/00 , G06F11/00 , G11B5/00
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

10. 发明授权

US08489946B2 Managing logically bad blocks in storage devices 有权
标题翻译：在存储设备中管理逻辑坏块
公开(公告)号：US08489946B2
公开(公告)日：2013-07-16
申请号：US13614805
申请日：2012-09-13
申请人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
发明人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
IPC分类号： G11C29/00
CPC分类号： G06F11/1092 , G06F2211/1057 , G06F2211/1059
摘要： At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.
摘要翻译：扫描存储设备的至少一个标准尺寸数据块以获得逻辑不良图案。如果检测到逻辑焊盘图案，则将与标准尺寸数据块相关联的块地址添加到坏块表。如果没有检测到逻辑填充图案，则可以确定与标准尺寸数据块相关联的块地址是否在坏块表中。如果没有检测到逻辑上的焊盘图案，并且如果与标准尺寸数据块相关联的块地址在坏块表中，则块地址可以从坏块表中去除。逻辑不良图案可以具有第一预定义数据部分和第二预定义数据部分，并且可以重复必需数量的实例以填充标准尺寸数据块。

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