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1. 发明授权

US08886881B2 Implementing storage adapter performance optimization with parity update footprint mirroring 有权
标题翻译：实现具有奇偶校验更新占用空间镜像的存储适配器性能优化
公开(公告)号：US08886881B2
公开(公告)日：2014-11-11
申请号：US13114268
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F11/20 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1076 , G06F11/1666 , G06F11/2089 , G06F11/2097 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059
摘要： A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有奇偶校验更新占用面积的双重适配器最小化固件操作之间的镜像，以及提供主题控制器电路所在的设计结构。第一控制器和第二控制器中的每一个包括多个硬件引擎，配置为存储奇偶校验更新占位（PUFP）数据的控制存储器; 数据存储和非易失性随机存取存储器（NVRAM）。一个控制器以第一启动器模式操作，用于将PUFP数据传送到以目标模式操作的另一个控制器。各启动器硬件引擎从启动器控制存储器传输PUFP数据，选择性地更新PUFP数据，并将PUFP数据写入发起者数据存储器和发起者NVRAM，同时将PUFP数据传输到另一个控制器。各个目标硬件引擎将PUFP数据写入目标数据存储和目标NVRAM，从而消除了固件操作。

2. 发明授权

US08516164B2 Implementing storage adapter performance optimization with enhanced hardware and software interface 失效
标题翻译：通过增强的硬件和软件接口实现存储适配器性能优化
公开(公告)号：US08516164B2
公开(公告)日：2013-08-20
申请号：US13114390
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F3/0689 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F11/108 , G06F2211/1009
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.
摘要翻译：一种用于实现具有链接硬件操作的存储适配器性能优化的方法和控制器以及最小化硬件和固件交互的增强的硬件（HW）和固件（FW）接口，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 和处理器。数据存储器被配置为存储多个控制块。全局工作队列包括选择性地布置在预定义链中以定义硬件操作序列的多个控制块。全局工作队列包括耦合到处理器和硬件引擎的队列输入以及耦合到硬件引擎的输出。控制块被布置在各自的引擎工作队列中，其被设计成控制各个硬件引擎的硬件操作，并且各个控制块被布置在事件队列中以向处理器提供完成结果。

3. 发明授权

US08495469B2 Implementing enhanced IO data conversion with protection information model including parity format of data integrity fields 有权
标题翻译：使用包括数据完整性字段奇偶校验格式的保护信息模型来实现增强的IO数据转换
公开(公告)号：US08495469B2
公开(公告)日：2013-07-23
申请号：US13108097
申请日：2011-05-16
申请人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
发明人： Brian E. Bakke , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Rick A. Weckwerth
IPC分类号： G06F12/00 , G06F11/00 , G11B5/00
CPC分类号： G06F11/1076
摘要： A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.
摘要翻译：一种用于通过增强的保护信息模型实现增强的输入/输出（IO）数据转换的方法和控制器，该增强的保护信息模型包括数据完整性字段（DIF）的增强的奇偶校验格式，以及提供了对象控制器电路所在的设计结构。控制器实现包括唯一奇偶校验数据完整性字段（DIF）格式的保护信息模型。唯一的奇偶校验DIF格式可以对RAID奇偶校验块进行故障检测。唯一奇偶校验DIF格式包括用于保护信息模型逻辑块保护循环冗余校验（CRC）字段和逻辑块参考标签（RT）字段的预定义大小。 RAID配置中的多个存储设备被耦合到控制器，并且被配置为存储数据和RAID奇偶校验冗余数据，并且其中当多个存储设备中的单个存储设备的丢失时，RAID奇偶校验冗余数据的强度不会降低存储设备发生。

4. 发明授权

US08495259B2 Implementing storage adapter performance optimization with hardware chains to select performance path 失效
标题翻译：使用硬件链实现存储适配器性能优化，以选择性能路径
公开(公告)号：US08495259B2
公开(公告)日：2013-07-23
申请号：US13114291
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moerti , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
摘要翻译：一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。每个预定义链定义一系列操作。每个控制块被设计成控制多个硬件引擎之一的硬件操作。资源句柄结构被配置为基于系统的特定特征来选择预定义的链。每个预定义链被配置为实现特定的性能路径以最大化性能。

5. 发明申请

US20120304198A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS 有权
标题翻译：实施存储适配器性能优化与链接硬件操作最小化硬件/固件交互
公开(公告)号：US20120304198A1
公开(公告)日：2012-11-29
申请号：US13114107
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F9/44
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有最小化硬件和固件交互的链接硬件操作，以及提供主题控制器电路驻留的设计结构。控制器包括多个硬件引擎; 和一个或多个处理器。事件队列被耦合到至少一个处理器通知多个预定义事件的处理器。控制块被设计成控制多个硬件引擎中的一个的操作，包括写入事件队列条目的硬件引擎。多个控制块被选择性地布置在预定义的链中以最小化硬件引擎将事件队列条目写入处理器。

6. 发明申请

US20120303855A1 IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA 失效
标题翻译：实施存储适配器性能优化与硬件加速器卸载固件，用于缓冲区分配和自动DMA
公开(公告)号：US20120303855A1
公开(公告)日：2012-11-29
申请号：US13114124
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.
摘要翻译：一种用于实现存储适配器性能优化的方法和控制器，其具有消除固件操作的自动链接硬件操作以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎和被配置为存储多个控制块的控制存储器。每个控制块被设计成控制多个硬件引擎之一的硬件操作。多个控制块被选择性地布置在相应的预定链中以定义硬件操作的顺序。自动硬件结构被配置为构建控制用于预定义硬件功能的硬件操作的相应预定义链。预定义的硬件功能包括从主机系统到控制器的写入操作的缓冲区分配和自动DMA数据，从而消除了固件操作。

7. 发明授权

US08301942B2 Managing possibly logically bad blocks in storage devices 有权
标题翻译：在存储设备中管理逻辑上坏的块
公开(公告)号：US08301942B2
公开(公告)日：2012-10-30
申请号：US12421671
申请日：2009-04-10
申请人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
发明人： Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl
IPC分类号： G11C29/00
CPC分类号： G06F11/1092 , G06F2211/1057 , G06F2211/1059
摘要： Methods and a computer program product related to the management of possibly logically bad blocks in storage devices are disclosed. A logically bad pattern is placed in a standard size data block if data associated with the data block has previously been stored or is waiting to be stored, but has subsequently become lost. The logical block address associated with the data block is stored in a bad block table. The possibly logically bad pattern is able to be detected, and the bad block table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given if the logical block address is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated to fill the standard size data block.
摘要翻译：公开了与存储设备中逻辑上不良块的管理相关的方法和计算机程序产品。如果与数据块相关联的数据先前已被存储或正在等待存储但随后丢失，则将标准尺寸数据块中的逻辑不良图案放置在标准尺寸数据块中。与数据块相关联的逻辑块地址存储在坏块表中。可以检测到可能的逻辑不良图案，并且检查坏块表以确定要读取的数据块是否实际上是逻辑错误的。如果逻辑块地址存在于坏块表中，则可以给出数据检查响应。可能逻辑上不良的图案可以具有第一预定义数据部分和第二预定义数据部分，并且可以重复以填充标准尺寸数据块。

8. 发明申请

US20100199039A1 Systems and Methods for Optimizing Host Reads and Cache Destages in a Raid System 审中-公开
标题翻译：在RAID系统中优化主机读取和高速缓存的系统和方法
公开(公告)号：US20100199039A1
公开(公告)日：2010-08-05
申请号：US12362828
申请日：2009-01-30
申请人： Scott A. Bauman , Brian Bowles , Robert E. Galbraith , Adrian C. Gerhard , Tim B. Lund
发明人： Scott A. Bauman , Brian Bowles , Robert E. Galbraith , Adrian C. Gerhard , Tim B. Lund
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F11/3433 , G06F11/3485 , G06F12/0866 , G06F2201/81 , G06F2201/885 , G06F2211/1009 , G06F2211/1057 , G06F2211/1059 , G06F2212/262
摘要： In one aspect, a method of a storage adapter controlling a redundant array of independent disks (RAID) may be provided. The method may include examining performance curves of a storage adapter with a write cache, determining if an amount of data entering the write cache of the storage adapter has exceeded a threshold, and implementing a strategy based on the determining operation. The strategy may include one of coupling Read-XOR/Write operations and providing priority reordering of Read operations over the Read-XOR/Write operations in order to minimize host read response time if data entering the write cache is less than the threshold, and allowing all Read operations and Read-XOR/Write operations to be queued at the device using simple tags in order to achieve maximum throughput if data entering the write cache is greater than the threshold. Additional aspects are described.
摘要翻译：一方面，可以提供控制独立磁盘冗余阵列（RAID）的存储适配器的方法。该方法可以包括使用写入高速缓存检查存储适配器的性能曲线，确定进入存储适配器的写入高速缓存的数据量是否已经超过阈值，以及基于确定操作来实现策略。该策略可以包括耦合Read-XOR / Write操作之一，并且通过Read-XOR / Write操作提供对Read操作的优先级重新排序，以便如果进入写高速缓存的数据小于阈值，则最小化主机读取响应时间，并允许所有Read操作和Read-XOR / Write操作在设备上使用简单标签进行排队，以便在输入写缓存的数据大于阈值时实现最大吞吐量。描述其他方面。

9. 发明授权

US5537567A Parity block configuration in an array of storage devices 失效
标题翻译：存储设备阵列中的奇偶校验块配置
公开(公告)号：US5537567A
公开(公告)日：1996-07-16
申请号：US212613
申请日：1994-03-14
申请人： Robert E. Galbraith , Joseph T. Writz
发明人： Robert E. Galbraith , Joseph T. Writz
IPC分类号： G06F12/16 , G06F3/06 , G06F11/10 , G06F11/14 , G11C29/00
CPC分类号： G06F11/1076
摘要： In a redundant array of disk storage units which independently accesses data blocks on different units and which uses parity blocks for data protection, parity blocks are confined to specific address ranges of each respective disk unit (rows of the array), each row containing multiple parity blocks. Each parity block represents the exclusive-OR of a stripe of data blocks located on a diagonal of the array. Where data accesses exhibit locality of reference in certain rows, this arrangement distributes the burden of updating parity more equally than a conventional RAID level 5. Additionally, because a "row" corresponds to a particular annular region of a disk surface on each respective disk unit, parity blocks can be located at optimal logical addresses or physical regions of the disk surface to simplify address translation and/or further improve performance.
摘要翻译：在独立访问不同单元上的数据块并使用奇偶校验块进行数据保护的磁盘存储单元的冗余阵列中，奇偶校验块被限制在每个相应磁盘单元（阵列的行）的特定地址范围内，每行包含多个奇偶校验块。每个奇偶校验块表示位于阵列对角线上的一条数据块的异或。在数据访问在某些行中显示参考的位置的情况下，这种布置比常规RAID级别5更均匀地分配更新奇偶校验的负担。另外，因为“行”对应于每个相应磁盘单元上的磁盘表面的特定环形区域，奇偶校验块可以位于磁盘表面的最佳逻辑地址或物理区域，以简化地址转换和/或进一步提高性能。

10. 发明授权

US08793462B2 Implementing storage adapter performance optimization with enhanced resource pool allocation 有权
标题翻译：通过增强资源池分配来实现存储适配器性能优化
公开(公告)号：US08793462B2
公开(公告)日：2014-07-29
申请号：US13114427
申请日：2011-05-24
申请人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
发明人： Brian E. Bakke , Brian L. Bowles , Michael J. Carnevale , Robert E. Galbraith, II , Adrian C. Gerhard , Murali N. Iyer , Daniel F. Moertl , Mark J. Moran , Gowrisankar Radhakrishnan , Rick A. Weckwerth , Donald J. Ziebarth
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0617 , G06F3/0631 , G06F3/0689
摘要： A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.
摘要翻译：一种用于实现具有增强的资源池分配的存储适配器性能优化的方法和控制器，以及提供主题控制器电路所在的设计结构。控制器包括多个硬件引擎; 处理器和多个资源池。多个工作队列与资源池相关联。处理器初始化类型列表，以及每种分配类型的相关联的页面数量。硬件引擎维护分配类型的计数，指定每个分配和解除分配的类型，并从资源池执行死锁避免的分配。

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