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1. 发明授权

US08908407B1 Content addressable memory (“CAM”) 有权
标题翻译：内容可寻址存储器（“CAM”）
公开(公告)号：US08908407B1
公开(公告)日：2014-12-09
申请号：US13548382
申请日：2012-07-13
申请人： Brent Steven Haukness , Mark D. Kellam
发明人： Brent Steven Haukness , Mark D. Kellam
IPC分类号： G11C15/00 , G11C15/04 , G11C15/02
CPC分类号： G11C15/046 , G11C15/02 , G11C15/04
摘要： A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.
摘要翻译：基于非常紧凑的设计的内容可寻址存储器件，每个存储器单元可能小到16F2。一个实施例基于具有两个存储器存储元件（诸如RRAM元件）的单元。每个RRAM元件和相应的FET串联在公共匹配线和相应的位线之间。每个单元的单元内容通过根据位值将电压施加到各个位线来匹配搜索字的位，并且使得每个单元的两个RRAM元件中的一个在低电阻路径上放电，细胞内容和位。如果对于一行的多个单元没有发生“快速”放电，则检测到匹配。此外，通过用特定字线电压控制FET，基本上消除了对高电压位线的匹配线再充电路径。

2. 发明申请

US20130242640A1 Methods and Systems for Resistive Change Memory Cell Restoration 审中-公开
标题翻译：电阻变化记忆细胞恢复的方法和系统
公开(公告)号：US20130242640A1
公开(公告)日：2013-09-19
申请号：US13789557
申请日：2013-03-07
申请人： Brent Steven Haukness , Mark D. Kellam
发明人： Brent Steven Haukness , Mark D. Kellam
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/72 , G11C2213/79
摘要： A resistive change memory device includes a first conductive line, a second conductive line, and a resistive change memory cell that includes a resistive memory element coupled between the first conductive line and the second conductive line. The resistive change memory device also includes control circuitry to apply, via the first conductive line and the second conductive line, a first biasing condition to the resistive change memory cell for a reset operation and a second biasing condition to the resistive change memory cell for a restore operation. The restore operation is performed to counteract a decrease in resistance of the resistive memory element for a reset state of the resistive change memory cell. At least one of a voltage, current, and duration of the second biasing condition is greater than a corresponding voltage, current, or duration of the first biasing condition.
摘要翻译：电阻变化存储器件包括第一导线，第二导线和电阻变化存储单元，其包括耦合在第一导线与第二导线之间的电阻性存储元件。电阻变化存储器件还包括控制电路，用于经由第一导线和第二导线将第一偏置状态施加到电阻变化存储单元以进行复位操作，并将第二偏置状态施加到电阻变化存储器单元恢复操作。执行恢复操作以抵消电阻式存储单元在电阻变化存储单元的复位状态下的电阻降低。第二偏置条件的电压，电流和持续时间中的至少一个大于第一偏置状态的对应的电压，电流或持续时间。

3. 发明申请

US20110286280A1 Pulse Control For NonVolatile Memory 有权
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：US20110286280A1
公开(公告)日：2011-11-24
申请号：US13146521
申请日：2010-01-29
申请人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当需要改变相关联的存储器单元中的状态时，存储器单元通道和参考电压（响应于位线选择）之间的耦合是脉冲式的。每个脉冲可以选择为小于约（20）纳秒，而脉冲之间的“休止期”通常被选择为约百纳秒或更大（例如，一微秒）的数量级。由于使用位线控制，所以可以启用非常短的上升时间，能够产生（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 如果需要，还可以使用分段字线或位线来最小化RC负载并且使足够短的上升时间使得脉冲变得坚固。

4. 发明授权

US08644078B2 Pulse control for nonvolatile memory 有权
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：US08644078B2
公开(公告)日：2014-02-04
申请号：US13146521
申请日：2010-01-29
申请人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

5. 发明授权

US09305644B2 Resistance memory cell 有权
标题翻译：电阻记忆单元
公开(公告)号：US09305644B2
公开(公告)日：2016-04-05
申请号：US14125913
申请日：2012-06-22
申请人： Mark D. Kellam , Gary Bela Bronner
发明人： Mark D. Kellam , Gary Bela Bronner
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0083 , G11C2213/72 , H01L27/2409 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143
摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
摘要翻译：电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。双端子存取装置影响电阻存储单元的电流 - 电压特性。电阻存储器还包括电路，跨越电阻存储单元施加具有设定极性的设定脉冲，以将电阻存储单元设置为在施加设置脉冲之后保持的低电阻状态，具有复位极性的复位脉冲与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态的电阻存储单元，而不改变电阻存储单元的电阻状态。

6. 发明申请

US20100207189A1 NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME 审中-公开
标题翻译：具有减少写入周期时间的非易失性存储器件
公开(公告)号：US20100207189A1
公开(公告)日：2010-08-19
申请号：US12669157
申请日：2008-05-20
申请人： Mark D. Kellam
发明人： Mark D. Kellam
IPC分类号： H01L29/788 , H01L21/31
CPC分类号： H01L29/7883 , H01L29/0649 , H01L29/512 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region.
摘要翻译：晶体管包括具有表面的衬底，其中衬底的第一区域和第二区域掺杂有第一类型的掺杂剂，并且其中第一区域和第二区域之间的衬底的第三区域掺杂有第二区域掺杂剂类型。在包括第三区域的表面的一部分上方沉积绝缘体层，并且在绝缘体层上方沉积栅极层。封装层封闭栅极层的端部，从而在绝缘体层的端部和封装层之间限定间隙。这些间隙具有相对于栅极层的端部的深度，绝缘体层的一端靠近第一区域和第三区域之间的边界，绝缘体层的另一端靠近第二区域和第二区域之间的边界第三区。

7. 发明授权

US06222279B1 Solder bump fabrication methods and structures including a titanium barrier layer 失效
标题翻译：包括钛阻挡层的焊点制造方法和结构
公开(公告)号：US06222279B1
公开(公告)日：2001-04-24
申请号：US09063422
申请日：1998-04-20
申请人： Joseph Daniel Mis , Gretchen Maerker Adema , Mark D. Kellam , W. Boyd Rogers
发明人： Joseph Daniel Mis , Gretchen Maerker Adema , Mark D. Kellam , W. Boyd Rogers
IPC分类号： H01L2348
CPC分类号： H01L24/03 , H01L21/2885 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/10145 , H01L2224/11001 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/11849 , H01L2224/13116 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.
摘要翻译：一种用于在具有接触焊盘的微电子器件上制造焊料凸块的方法包括以下步骤：在该器件上沉积钛阻挡层，在该钛阻挡层上形成凸块下的冶金层，以及在该凸起下的冶金学上形成一个或多个焊料凸点层。焊料凸块或凸点限定突出的冶金层的暴露部分被去除，然后去除钛阻挡层的暴露部分。钛阻挡层保护下面的微电子器件不被用于去除凸块下金属层的蚀刻剂。钛层还防止下凸块冶金层在下面的微电子器件上形成残留物。因此，钛阻挡层允许下凸块冶金层快速去除而不留下残留物，从而减少焊料凸块之间的电短路的可能性。

8. 发明申请

US20100025811A1 INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION 审中-公开
标题翻译：具有内置加热电路的集成电路反向运行变化
公开(公告)号：US20100025811A1
公开(公告)日：2010-02-04
申请号：US12516499
申请日：2007-11-29
申请人： Gary Bronner , Brent S. Haukness , Fariborz Assaderaghi , Mark D. Kellam , Mark Horowitz
发明人： Gary Bronner , Brent S. Haukness , Fariborz Assaderaghi , Mark D. Kellam , Mark Horowitz
IPC分类号： H01L23/34
CPC分类号： H01L27/105 , H01L21/67103 , H01L23/345 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).
摘要翻译：集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。存储器件的字线或位线用作加热元件（107）。

9. 发明申请

US20120211722A1 THREE-DIMENSIONAL MEMORY ARRAY STACKING STRUCTURE 有权
标题翻译：三维存储阵列堆叠结构
公开(公告)号：US20120211722A1
公开(公告)日：2012-08-23
申请号：US13505442
申请日：2010-08-26
申请人： Mark D. Kellam , Gary B. Bronner
发明人： Mark D. Kellam , Gary B. Bronner
IPC分类号： H01L45/00
CPC分类号： G11C5/063 , G11C5/02 , H01L27/2409 , H01L27/2418 , H01L27/2454 , H01L27/249 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146
摘要： A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
摘要翻译：存储装置包括平面基板，平面基板上方的多个水平导电平面以及与多个水平导电平面交错的多个水平绝缘层。垂直于多个导电平面和绝缘层的垂直导电柱阵列穿过多个导电平面和绝缘层中的孔。存储器件包括多个可编程存储器元件，每个可编程存储器元件将一个水平导电平面耦合到相应的垂直导电柱。

10. 发明授权

US6025767A Encapsulated micro-relay modules and methods of fabricating same 失效
标题翻译：封装的微型继电器模块及其制造方法
公开(公告)号：US6025767A
公开(公告)日：2000-02-15
申请号：US692502
申请日：1996-08-05
申请人： Mark D. Kellam , Michele J. Berry
发明人： Mark D. Kellam , Michele J. Berry
IPC分类号： B81B3/00 , B81C1/00 , B81C3/00 , H01H1/66 , H01H11/00 , H01H45/02 , H01H50/00 , H01H50/02 , H01H67/02
CPC分类号： H01H50/005 , H01H1/66 , H01H2050/025
摘要： A micro-relay module includes a substrate and a lid in spaced apart relation, and a solder ring which bonds the lid to the substrate to define a chamber therebetween. A micromachined relay is integrally formed on the substrate or on the lid within the chamber. A gas is contained in the chamber at a gas pressure which is above atmospheric pressure. Input/output pads are included outside the chamber and electrically connected to the micromachined relay. Large numbers of encapsulated modules may be fabricated on a single substrate by integrally forming an array of relays on a face of a first substrate. A second substrate is placed adjacent the face with a corresponding array of solder rings therebetween, such that a respective solder ring surrounds a respective relay. The solder rings are reflowed in a gas atmosphere which is above atmospheric pressure to thereby form an array of high pressure gas encapsulating chambers. The first and second substrates are then singulated for form a plurality of individual micro-relay modules.
摘要翻译：微型继电器模块包括基板和间隔开的盖子，以及焊接环，其将盖子结合到基板以在其间限定室。微机械继电器一体地形成在基板上或室内的盖上。气体在高于大气压的气体压力下容纳在腔室中。输入/输出焊盘包括在室外，并电连接到微加工继电器。通过在第一衬底的表面上整合形成继电器阵列，可以在单个衬底上制造大量的封装模块。第二衬底被放置成与面对相邻的焊接环阵列相邻，使得相应的焊锡环围绕相应的继电器。焊锡环在高于大气压的气体气氛中回流，从而形成高压气体封装室阵列。然后将第一和第二衬底分成多个单独的微型继电器模块。

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