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1. 发明授权

US08492820B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08492820B2
公开(公告)日：2013-07-23
申请号：US13406664
申请日：2012-02-28
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/94
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

2. 发明申请

US20120153431A1 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
标题翻译：集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法
公开(公告)号：US20120153431A1
公开(公告)日：2012-06-21
申请号：US13406664
申请日：2012-02-28
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

3. 发明授权

US08193067B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08193067B2
公开(公告)日：2012-06-05
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L21/20
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

4. 发明申请

US20110133310A1 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
标题翻译：集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法
公开(公告)号：US20110133310A1
公开(公告)日：2011-06-09
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/92 , H01L21/8242
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

5. 发明申请

US20110180862A1 EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
标题翻译：嵌入式动态随机访问存储器件和方法
公开(公告)号：US20110180862A1
公开(公告)日：2011-07-28
申请号：US12692760
申请日：2010-01-25
申请人： Brent A. Anderson , John E. Barth, JR. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
发明人： Brent A. Anderson , John E. Barth, JR. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
IPC分类号： H01L27/12 , H01L27/108 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
摘要翻译：本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法晶圆。本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

6. 发明授权

US09059319B2 Embedded dynamic random access memory device and method 有权
标题翻译：嵌入式动态随机存取存储器件及方法
公开(公告)号：US09059319B2
公开(公告)日：2015-06-16
申请号：US12692760
申请日：2010-01-25
申请人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
发明人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
IPC分类号： H01L27/108 , H01L21/84 , H01L29/66
CPC分类号： H01L21/84 , H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
摘要翻译：本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法晶圆。本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

7. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

8. 发明授权

US08946045B2 Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI) 有权
标题翻译：具有深沟槽（DT）结构的金属绝缘体金属（MIM）电容器和绝缘体上硅（SOI）
公开(公告)号：US08946045B2
公开(公告)日：2015-02-03
申请号：US13457601
申请日：2012-04-27
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/02
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
摘要翻译：公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。该结构包括具有金属层和至少一个电介质层的多层基底。沟槽被蚀刻到衬底中，穿过金属层。沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。电介质材料将沟槽中的金属材料排列。沟槽填充有导体。将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。导体包括电容器的第二节点。

9. 发明授权

US08586444B2 Creating deep trenches on underlying substrate 有权
标题翻译：在底层基底上创造深沟
公开(公告)号：US08586444B2
公开(公告)日：2013-11-19
申请号：US13428004
申请日：2012-03-23
申请人： Jennifer E. Appleyard , John E. Barth, Jr. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
发明人： Jennifer E. Appleyard , John E. Barth, Jr. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/76898 , H01L27/0805 , H01L28/91 , H01L29/945
摘要： A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
摘要翻译：公开了半导体结构及其制造方法。在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。第一氧化物层设置在第一衬底上。可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

10. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

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