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1. 发明授权

US06579625B1 Magnetoelectronics element having a magnetic layer formed of multiple sub-element layers 失效
标题翻译：具有由多个子元件层形成的磁性层的磁电元件
公开(公告)号：US06579625B1
公开(公告)日：2003-06-17
申请号：US09695467
申请日：2000-10-24
申请人： Bradley N. Engel , Nicholas D. Rizzo , Jason A. Janesky , Saied Tehrani
发明人： Bradley N. Engel , Nicholas D. Rizzo , Jason A. Janesky , Saied Tehrani
IPC分类号： G11B5127
CPC分类号： H01F10/3254 , B82Y10/00 , B82Y25/00 , G11C11/16 , H01F10/32 , H01L27/222 , H01L43/08 , Y10T428/1171 , Y10T428/12465 , Y10T428/12639 , Y10T428/24942 , Y10T428/31
摘要： A magnetic layer (46) of a magnetoelectronics element (40) is provided that has a first sub-element layer (48) and a second sub-element layer (50). The first sub-element layer (48) is configured to have a first area and the second sub-element layer (50) is configured to have a second area that is less than the first area.
摘要翻译：提供了具有第一子元件层（48）和第二子元件层（50）的磁电元件（40）的磁性层（46）。第一子元件层（48）被配置为具有第一区域，并且第二子元件层（50）被配置为具有小于第一区域的第二区域。

2. 发明授权

US06888743B2 MRAM architecture 有权
标题翻译： MRAM架构
公开(公告)号：US06888743B2
公开(公告)日：2005-05-03
申请号：US10331058
申请日：2002-12-27
申请人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
发明人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
IPC分类号： G11C11/15 , G11C11/02
CPC分类号： G11C11/16
摘要： An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要翻译：提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。

3. 发明授权

US06909631B2 MRAM and methods for reading the MRAM 有权
标题翻译： MRAM和读取MRAM的方法
公开(公告)号：US06909631B2
公开(公告)日：2005-06-21
申请号：US10679134
申请日：2003-10-02
申请人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
发明人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
IPC分类号： G11C11/15 , G11C11/16 , G11C11/14
CPC分类号： G11C11/16 , G11C11/15
摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
摘要翻译：提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。

4. 发明授权

US08228715B2 Structures and methods for a field-reset spin-torque MRAM 失效
标题翻译：现场复位自旋扭矩MRAM的结构和方法
公开(公告)号：US08228715B2
公开(公告)日：2012-07-24
申请号：US12789838
申请日：2010-05-28
申请人： Thomas Andre , Saied Tehrani , Jon Slaughter , Nicholas Rizzo
发明人： Thomas Andre , Saied Tehrani , Jon Slaughter , Nicholas Rizzo
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/1657 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.
摘要翻译：编程自旋转矩磁阻存储器阵列的装置和方法包括位于多个磁阻位中的每一个附近的金属复位线，并且被配置为通过在电流下产生磁场将多个磁阻存储元件设置为已知状态流过它然后将自旋转矩传递电流施加到选定的磁阻位，以将所选位切换到编程状态。在另一种操作模式中，在产生磁场之前感测到多个位的电阻。在产生磁场之后再次感测电阻，并且根据电阻变化确定由每个位的初始状态表示的数据。然后，自旋转矩传递电流仅施加于具有与施加磁场之前不同的电阻的那些磁阻位。

5. 发明授权

US06205052B1 Magnetic element with improved field response and fabricating method thereof 有权
标题翻译：具有改善的场响应的磁性元件及其制造方法
公开(公告)号：US06205052B1
公开(公告)日：2001-03-20
申请号：US09422447
申请日：1999-10-21
申请人： Jon Slaughter , Jing Shi , Eugene Chen , Saied Tehrani
发明人： Jon Slaughter , Jing Shi , Eugene Chen , Saied Tehrani
IPC分类号： G11C1115
CPC分类号： H01L43/08 , B82Y25/00 , H01F10/324 , H01F10/3254 , H01F10/3268
摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26). A second electrode (18) is included and comprises a free ferromagnetic layer (28). A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16). At least one additional layer (20 & 22) is provided between the base metal layer (13) and the spacer layer (16). The base metal layer (13) or at least one of the layers positioned between the base metal layer (13) and the spacer layer (16) having an x-ray amorphous structure such that a reduced topological coupling strength between the free ferromagnetic layer (28) and the fixed ferromagnetic layer (26) is achieved.
摘要翻译：一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。第一电极（14）包括固定的铁磁层（26）。包括第二电极（18）并且包括自由铁磁层（28）。间隔层（16）位于固定铁磁层（26）和自由铁磁（28）层间隔层（16）之间。至少一个附加层（20和22）设置在基底金属层（13）和间隔层（16）之间。基底金属层（13）或位于基底金属层（13）和间隔层（16）之间的层中的至少一层具有x射线非晶结构，使得游离铁磁层（ 28）和固定铁磁层（26）。

6. 发明授权

US5412224A Field effect transistor with non-linear transfer characteristic 失效
标题翻译：具有非线性传输特性的场效应晶体管
公开(公告)号：US5412224A
公开(公告)日：1995-05-02
申请号：US894989
申请日：1992-06-08
申请人： Herbert Goronkin , Jun Shen , Saied Tehrani
发明人： Herbert Goronkin , Jun Shen , Saied Tehrani
IPC分类号： H01L29/80 , H01L29/10 , H01L29/778 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/1029 , H01L29/1054 , H01L29/778
摘要： A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a N-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned to provide self-doping by electrons in the valence band of the P-channel (14) moving to the conduction band of the N-channels (12, 16) providing peak channel conductivity. At higher gate bias, one of the N-channels (12) becomes non-conductive creating a negative resistance region.
摘要翻译：提供了具有由包括宽带隙材料（18）的阻挡层隔开的多个垂直堆叠通道（12,14,16）的场效应半导体器件。通道（12,14,16）形成在宽带隙缓冲层（11）上，每个通道耦合有N型漏区（22b）。每个通道也耦合到N型源极区域（25b）。在栅电极（17）上具有合适的栅极偏置，通道（12,14,16）中的量化能级被对准以提供通过移动到导通的P沟道（14）的价带中的电子的自掺杂带宽的N沟道（12,16）提供峰值沟道导电性。在较高的栅极偏压下，N沟道（12）中的一个变为不导通，产生负电阻区域。

7. 发明授权

US5289014A Semiconductor device having a vertical quantum well via and method for making 失效
标题翻译：具有垂直量子阱的半导体器件及其制造方法
公开(公告)号：US5289014A
公开(公告)日：1994-02-22
申请号：US930958
申请日：1992-08-17
申请人： Herbert Goronkin , Jun Shen , Saied Tehrani , X. Theodore Zhu
发明人： Herbert Goronkin , Jun Shen , Saied Tehrani , X. Theodore Zhu
IPC分类号： H01L21/20 , H01L29/06 , H01L29/76 , H01L29/80 , H01L29/161 , H01L29/205
CPC分类号： B82Y10/00 , H01L29/7613
摘要： A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).
摘要翻译：提供了具有由包括半导体材料的量子阱形成的垂直互连或通过层叠形成的半导体器件。具有载流区域（19）的第一半导体器件（11）形成在第一水平面中。具有载流区域（29）的第二半导体器件（12）形成在第二水平面中。每个电流承载区域具有基本相等的第一量化能级。半导体通孔（31）将第一半导体器件（11）的载流区域（19）耦合到第二器件（12）的载流区域（29），其中半导体通孔（31）具有第一量子化能能够与第一和第二半导体器件（11,12）的载流区域（19,29）的量化能级对准。

8. 发明授权

US06544801B1 Method of fabricating thermally stable MTJ cell and apparatus 有权
标题翻译：制造热稳定MTJ电池及其装置的方法
公开(公告)号：US06544801B1
公开(公告)日：2003-04-08
申请号：US09642350
申请日：2000-08-21
申请人： Jon Slaughter , Saied Tehrani , Eugene Chen , Mark Durlam , Mark DeHerrera , Renu Whig Dave
发明人： Jon Slaughter , Saied Tehrani , Eugene Chen , Mark Durlam , Mark DeHerrera , Renu Whig Dave
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00
摘要： An MTJ cell including an insulator layer of material between magnetic material layers with the insulator layer of material having a greater attraction for a third material than the magnetic material layers. The third material is introduced to one or both so that when the cell is heated the third material is redistributed from the magnetic material layer to the insulator layer. Upon redistribution the insulator layer becomes an insulator layer material. Also, a first diffusion barrier layer is positioned between a first metal electrode and one of the magnetic material layers and/or a second diffusion barrier layer is positioned between a second metal electrode and the other magnetic material layer to prevent diffusion of the metal in the electrodes into the magnetic material layers.
摘要翻译： MTJ单元包括在磁性材料层之间的材料的绝缘体层，材料的绝缘体层对于第三材料具有比磁性材料层更大的吸引力。将第三材料引入一个或两个，使得当电池被加热时，第三材料从磁性材料层重新分布到绝缘体层。在再分配时，绝缘体层变成绝缘体层材料。此外，第一扩散阻挡层位于第一金属电极和一个磁性材料层之间，和/或第二扩散阻挡层位于第二金属电极和另一个磁性材料层之间，以防止金属在电极进入磁性材料层。

9. 发明授权

US06365419B1 High density MRAM cell array 失效
标题翻译：高密度MRAM单元阵列
公开(公告)号：US06365419B1
公开(公告)日：2002-04-02
申请号：US09649114
申请日：2000-08-28
申请人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
发明人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/12
摘要： A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.
摘要翻译：制造MRAM单元的方法包括在半导体衬底上提供隔离晶体管，并在衬底上形成与晶体管的一个端子连通的互连叠层。通孔形成在堆叠的上端，以从数字线下方的位置延伸到数字线上方的位置。通孔也延伸到电介质层的上表面之上，以提供对准键。 MTJ存储单元位于与通孔接触的上表面上，并且通过使用侧壁间隔件和选择性蚀刻，磁性材料的自由层的端部与磁性材料的被钉扎边缘的端部间隔开。

10. 发明授权

US06285581B1 MRAM having semiconductor device integrated therein 有权
标题翻译：集成了半导体器件的MRAM
公开(公告)号：US06285581B1
公开(公告)日：2001-09-04
申请号：US09460056
申请日：1999-12-13
申请人： Saied Tehrani , Jing Shi
发明人： Saied Tehrani , Jing Shi
IPC分类号： G11C1115
CPC分类号： G11C11/15 , H01L27/224 , H01L27/228
摘要： A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A magnetic layer (34) is positioned between the first ferromagnetic layer and a digit line (first) for pinning a magnetic vector within the second ferromagnetic layer. In a 13 embodiment, a gate contact (37) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.
摘要翻译：磁存储单元（10）具有位于形成p-n或肖特基结的第一（11）和第二（13）铁磁层之间的半导体层（12）。磁性层（34）位于第一铁磁层和数字线（第一）之间，用于固定第二铁磁层内的磁矢量。在13实施例中，栅极接触（37）与半导体材料层间隔开，用于控制通过半导体层的电子流。

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