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1. 发明授权

US06365419B1 High density MRAM cell array 失效
标题翻译：高密度MRAM单元阵列
公开(公告)号：US06365419B1
公开(公告)日：2002-04-02
申请号：US09649114
申请日：2000-08-28
申请人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
发明人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/12
摘要： A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.
摘要翻译：制造MRAM单元的方法包括在半导体衬底上提供隔离晶体管，并在衬底上形成与晶体管的一个端子连通的互连叠层。通孔形成在堆叠的上端，以从数字线下方的位置延伸到数字线上方的位置。通孔也延伸到电介质层的上表面之上，以提供对准键。 MTJ存储单元位于与通孔接触的上表面上，并且通过使用侧壁间隔件和选择性蚀刻，磁性材料的自由层的端部与磁性材料的被钉扎边缘的端部间隔开。

2. 发明授权

US06331943B1 MTJ MRAM series-parallel architecture 失效
标题翻译： MTJ MRAM系列并行架构
公开(公告)号：US06331943B1
公开(公告)日：2001-12-18
申请号：US09649117
申请日：2000-08-28
申请人： Peter K. Naji , Mark DeHerrera , Mark Durlam
发明人： Peter K. Naji , Mark DeHerrera , Mark Durlam
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/15
摘要： Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.
摘要翻译：磁性隧道结随机存取存储器结构，其中存储器单元阵列以行和列排列，并且每个存储单元包括并行连接的磁性隧道结和控制晶体管。控制线连接到一排控制晶体管中的每个控制晶体管的栅极，并且与每个磁性隧道结相邻的金属编程线通过通孔以间隔开的间隔连接到控制线。此外，每列中的存储单元组被串联连接以形成与全局位线并行连接的局部位线。使用位于中心的列来读取串并联配置以提供参考信号，并且将参考列的每一侧的列中的数据与参考信号进行比较或差异地比较两个接近的列。

3. 发明授权

US5831920A GMR device having a sense amplifier protected by a circuit for dissipating electric charges 失效
标题翻译： GMR器件具有由用于耗散电荷的电路保护的读出放大器
公开(公告)号：US5831920A
公开(公告)日：1998-11-03
申请号：US949605
申请日：1997-10-14
申请人： Eugene Chen , Saied N. Tehrani , Mark Durlam , Peter K. Naji
发明人： Eugene Chen , Saied N. Tehrani , Mark Durlam , Peter K. Naji
IPC分类号： G11C11/16 , G11C7/00
CPC分类号： G11C11/16
摘要： A new and improved magnetic device is provided for memories and sensors. A magnetic random access memory (MRAM) device (20) includes a storage element (21) for magnetically storing states and an amplifier (25) for sensing the states stored in the storage element. A circuit (27) for dissipating electrical charges are coupled to inputs (23,24) of the amplifier (25) to discharge electrical charges applied to the inputs (23,24) of the amplifier (25). The charge dissipating circuit (27) includes junctions (271-274) which are typically connected in series between power (255) and common (257) lines. Electric charges applied to the inputs (23,24) of the amplifier (25) is discharged through the junctions (271-274).
摘要翻译：为存储器和传感器提供了一种新的改进的磁性器件。磁性随机存取存储器（MRAM）装置（20）包括用于磁存储状态的存储元件（21）和用于感测存储在存储元件中的状态的放大器（25）。用于耗散电荷的电路（27）耦合到放大器（25）的输入（23,24），以放电施加到放大器（25）的输入端（23,24）的电荷。电荷消耗电路（27）包括通常在功率（255）和公共（257）线之间串联连接的结（271-274）。施加到放大器（25）的输入端（23,24）的电荷通过接点（271-274）放电。

4. 发明授权

US06452823B1 Non-volatile magnetic cache memory and method of use 有权
标题翻译：非易失磁磁存储器及其使用方法
公开(公告)号：US06452823B1
公开(公告)日：2002-09-17
申请号：US09774983
申请日：2001-01-31
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1502
CPC分类号： G11C15/02 , G06F12/0802 , G06F12/0895 , G06F2212/222 , G11C15/046
摘要： A non-volatile, bistable magnetic tunnel junction cache memory including a cache tag array and a cache data array. The cache tag array includes non-volatile magnetic memory tag cells arranged in rows and columns. Each row of the tag array includes a word line and a digit line associated with each tag cell in the row. The cache data array includes non-volatile magnetic memory data cells arranged in rows and columns. The rows of the data array correspond with the rows of the tag array and each row of the data array is magnetically associated with the word line and the digit line associated with each corresponding row of the tag array.
摘要翻译：包括高速缓存标签阵列和高速缓存数据阵列的非易失性，双稳态磁隧道结缓存存储器。高速缓存标签阵列包括排列成行和列的非易失性磁记录标签单元。标签阵列的每一行包括与行中的每个标记单元相关联的字线和数字线。高速缓存数据阵列包括以行和列排列的非易失性磁存储器数据单元。数据阵列的行对应于标签阵列的行，并且数据阵列的每一行与字线和与标签阵列的每个对应行相关联的数字线磁性地相关联。

5. 发明授权

US06304477B1 Content addressable magnetic random access memory 有权
标题翻译：内容可寻址磁性随机存取存储器
公开(公告)号：US06304477B1
公开(公告)日：2001-10-16
申请号：US09774934
申请日：2001-01-31
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1502
CPC分类号： G11C15/046 , G11C15/02
摘要： A content addressable magnetic random access memory cell including a differentially connected pair of MTJs and comparison and match detection circuitry connected to the MTJs and including differential tag bitlines, differential tag program bitlines, an enable line, a word line, a digit line, and a match line. The match line provides an indication of a match between input data placed on the differential tag bitlines and stored data in the cell.
摘要翻译：一种内容可寻址磁性随机存取存储单元，包括差分连接的一对MTJ和连接到MTJ的比较和匹配检测电路，并且包括差分标签位线，差分标签程序位线，使能线，字线，数字线和匹配线。匹配线提供放置在差分标签位线上的输入数据与单元格中存储的数据之间的匹配的指示。

6. 发明授权

US06169689A MTJ stacked cell memory sensing method and apparatus 有权
标题翻译： MTJ堆叠式电池存储器感应方法及装置
公开(公告)号：US06169689A
公开(公告)日：2001-01-02
申请号：US09456615
申请日：1999-12-08
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C907
CPC分类号： G11C11/15 , G11C11/5607 , G11C2211/5615
摘要： Apparatus and method of reading the state of each cell in a stacked memory comprising stacks of cells in an addressable array with each stack including MTJ memory cells stacked together with current terminals connected in series, and including a first and second current terminals coupled through an electronic switch to a current source. Each stack includes 2n levels of memory. A voltage drop across an addressed stack is sensed. Reference voltages equal to the 2n memory levels are provided and the sensed voltage drop is compared to the reference voltages to determine the memory level in the addressed stack. Encoding apparatus is used to convert the voltage drop to a digital output signal.
摘要翻译：读取堆叠存储器中每个单元的状态的装置和方法，包括可寻址阵列中的单元堆叠，每个堆叠包括与串联连接的当前端子堆叠的MTJ存储器单元，并且包括通过电子耦合的第一和第二电流端子切换到当前源。每个堆栈包括2n级存储器。感测到寻址堆栈的电压降。提供等于2n个存储器电平的参考电压，并将所感测的电压降与参考电压进行比较，以确定寻址堆叠中的存储器电平。编码装置用于将电压降转换为数字输出信号。

7. 发明授权

US5986925A Magnetoresistive random access memory device providing simultaneous reading of two cells and operating method 失效
标题翻译：提供同时读取两个单元的磁阻随机存取存储器件和操作方法
公开(公告)号：US5986925A
公开(公告)日：1999-11-16
申请号：US55731
申请日：1998-04-07
申请人： Peter K. Naji , Russell G. Byrd
发明人： Peter K. Naji , Russell G. Byrd
IPC分类号： G11C11/15 , G11C11/56 , G11C11/00
CPC分类号： G11C11/5607 , G11C11/15 , G11C2211/5615
摘要： A magnetoresistive random access memory (MRAM) having a novel circuit configuration (40) is provided. The MRAM device includes a plurality of magnetic memory cells in a memory array (41). The magnetic memory cell includes magnetoresistive layers separated by an insulating layer which forms a tunneling junction between the magnetoresistive layers. A sense line selector (42, 43) selects two memory cells (48) in which a sense current (66) is applied from a current source (45). Voltages generated over the memory cells are sensed and compared to predetermined threshold voltages to provide outputs (OUT1, OUT2) which correspond to states stored in the pair of the memory cells (48). This new MRAM device attains non-volatile random access memory with high-speed and high-density.
摘要翻译：提供具有新颖电路结构（40）的磁阻随机存取存储器（MRAM）。 MRAM设备包括存储器阵列（41）中的多个磁存储单元。磁存储单元包括通过在磁阻层之间形成隧道结的绝缘层分开的磁阻层。感测线选择器（42,43）选择其中从电流源（45）施加感测电流（66）的两个存储单元（48）。检测在存储器单元上产生的电压并将其与预定阈值电压进行比较，以提供对应于存储在该对存储单元（48）中的状态的输出（OUT1，OUT2）。这种新的MRAM器件实现了高速，高密度的非易失性随机存取存储器。

8. 发明授权

US06445612B1 MRAM with midpoint generator reference and method for readout 有权
标题翻译：具有中点发生器参考的MRAM和读出方法
公开(公告)号：US06445612B1
公开(公告)日：2002-09-03
申请号：US09940320
申请日：2001-08-27
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： The MRAM architecture includes a data column of memory cells and a reference column, including a midpoint generator, positioned adjacent the data column on a substrate. The memory cells and the midpoint generator include similar magnetoresistive memory elements, e.g. MTJ elements. The MTJ elements of the generator are each set to one of Rmax and Rmin and connected together to provide a total resistance of a midpoint between Rmax and Rmin. A differential read-out circuit is coupled to the data column and to the reference column for differentially comparing a data voltage to a reference voltage.
摘要翻译： MRAM架构包括存储器单元的数据列和与基板上的数据列相邻定位的参考列，包括中点发生器。存储器单元和中点发生器包括类似的磁阻存储元件，例如， MTJ元素。发电机的MTJ元件分别设置为Rmax和Rmin中的一个，并连接在一起以提供Rmax和Rmin之间的中点的总电阻。差分读出电路耦合到数据列和参考列，用于将数据电压与参考电压进行差分比较。

9. 发明授权

US06385109B1 Reference voltage generator for MRAM and method 失效
标题翻译： MRAM参考电压发生器及方法
公开(公告)号：US06385109B1
公开(公告)日：2002-05-07
申请号：US09772668
申请日：2001-01-30
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1100
CPC分类号： G11C5/147 , G11C11/15 , G11C11/16
摘要： Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2) (1+Rmin/Rmax) where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell. A reference voltage generator is disclosed which generates the reference voltage and includes an operational amplifier and two MTJ memory cells connected to provide an output signal equal to (Vbias1/2) (1+Rmin/Rmax)
摘要翻译：公开了用于磁隧道结（MTJ）存储单元或MTJ存储单元阵列的读出电路，其需要等于（Vbias1 / 2）（1 + Rmin / Rmax）的变化的参考电压，其中Vbias1是施加的钳位电压到读出电路，Rmin是磁性隧道结存储单元的最小电阻，Rmax是磁性隧道结存储单元的最大电阻。公开了一种参考电压发生器，其产生参考电压并且包括运算放大器和两个连接以提供等于（Vbias1 / 2）（1 + Rmin / Rmax）的输出信号的MTJ存储器单元，

10. 发明授权

US06272041B1 MTJ MRAM parallel-parallel architecture 有权
标题翻译： MTJ MRAM并行架构
公开(公告)号：US06272041B1
公开(公告)日：2001-08-07
申请号：US09649562
申请日：2000-08-28
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1114
CPC分类号： G11C11/15 , H01L27/228
摘要： Magnetic tunnel junction random access memory parallel-parallel architecture wherein an array of memory cells is arranged in rows and columns with each memory cell including a magnetic tunnel junction and a control transistor connected in series. The array of memory cells is constructed with a plurality of columns and each column includes a global bit line coupled to a control circuit. Each column further includes a plurality of local bit lines coupled in parallel to the global bit line and a plurality of groups of memory cells, with each group including a plurality of memory cells connected in parallel between the local bit line and a reference potential.
摘要翻译：磁性隧道结随机存取存储器并行架构，其中存储单元阵列以行和列排列，每个存储单元包括磁性隧道结和串联连接的控制晶体管。存储单元的阵列由多个列构成，并且每列包括耦合到控制电路的全局位线。每列还包括与全局位线并联耦合的多个局部位线和多个存储单元组，每组具有并联连接在局部位线和参考电位之间的多个存储单元。

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