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1. 发明授权

US08429491B1 Methods and apparatus for error checking code decomposition 有权
公开(公告)号：US08429491B1
公开(公告)日：2013-04-23
申请号：US12623122
申请日：2009-11-20
申请人： Gregg William Baeckler , Babette Van Antwerpen
发明人： Gregg William Baeckler , Babette Van Antwerpen
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.

2. 发明授权

US08166427B1 Tracing and reporting registers removed during synthesis 有权
标题翻译：在合成期间删除跟踪和报告记录
公开(公告)号：US08166427B1
公开(公告)日：2012-04-24
申请号：US12044926
申请日：2008-03-07
申请人： Swatiben Ruturaj Pathak , Babette Van Antwerpen , Michael D. Hutton , Andrew Leaver
发明人： Swatiben Ruturaj Pathak , Babette Van Antwerpen , Michael D. Hutton , Andrew Leaver
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.
摘要翻译：跟踪在电子电路合成过程中去除寄存器或其他电路的原因和结果的电路，方法，软件和设备。本发明的示例性实施例跟踪寄存器的移除并确定为什么寄存器被去除。然后以有效的方式提供该信息用于设计调试目的。

3. 发明授权

US08108812B1 Register retiming technique 有权
标题翻译：注册重新定时技术
公开(公告)号：US08108812B1
公开(公告)日：2012-01-31
申请号：US12749514
申请日：2010-03-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

4. 发明授权

US07689955B1 Register retiming technique 失效
标题翻译：注册重新定时技术
公开(公告)号：US07689955B1
公开(公告)日：2010-03-30
申请号：US11513450
申请日：2006-08-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

5. 发明授权

US07171633B1 Estimating quality during early synthesis 有权
标题翻译：早期综合评估质量
公开(公告)号：US07171633B1
公开(公告)日：2007-01-30
申请号：US10734905
申请日：2003-12-12
申请人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
发明人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmable logic integrated circuit. In a specific implementation, the invention incorporates late-stage synthesis operations, such as found during a technology mapping operation, into earlier stage synthesis procedures. These late-stage synthesis operations are used to provide better estimates of delay and area of a final compiled design in order to guide optimization operations.
摘要翻译：计算机辅助系统包括提高逻辑功能的合成和映射到诸如可编程逻辑的逻辑单元（例如，查找表）的目标技术的逻辑结构中的精度，优化和最小化的方法集成电路。在具体实现中，本发明将晚期合成操作（诸如在技术映射操作期间发现）融入到早期阶段合成过程中。这些后期综合操作用于提供对最终编译设计的延迟和面积的更好估计，以指导优化操作。

6. 发明授权

US07945877B1 Recognizing muliplexers 有权
标题翻译：识别多路复用器
公开(公告)号：US07945877B1
公开(公告)日：2011-05-17
申请号：US12041558
申请日：2008-03-03
申请人： Babette Van Antwerpen
发明人： Babette Van Antwerpen
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505
摘要： A chain of multiplexers disposed in a logic block is recognized as a selector and a group of logic gates disposed in the logic block and supplying signals to the select pins of the selector is recognized as a decoder, the selector and the decoder together define a n:1 multiplexer. To achieve this, a group of logic gates supplying signals to the select pins of the selector is identified within the logic block. A truth table defining the logic relationship between the signals applied to the group of logic gates and data signals received by the chain of muxes is generated. The chain of muxes is replaced with a selector upon determination that the rows in the truth table are disjoint. After replacing the chain of muxes with a selector, the process is repeated in a similar manner to replace the remaining logic blocks with a decoder.
摘要翻译：设置在逻辑块中的多路复用器链被识别为选择器，并且设置在逻辑块中的一组逻辑门并且向选择器的选择引脚提供信号被识别为解码器，选择器和解码器一起定义： 1多路复用器。为了实现这一点，在逻辑块内识别向选择器的选择引脚提供信号的一组逻辑门。产生一个真值表，其中定义了施加到逻辑门组的信号与多路复用器链接收的数据信号之间的逻辑关系。在确定真值表中的行是不相交的情况下，多路复用链被选择器替换。在用选择器替换多路复用链之后，以类似的方式重复该过程，以用解码器替换剩余的逻辑块。

7. 发明授权

US07418690B1 Local searching techniques for technology mapping 失效
标题翻译：技术测绘的本地搜索技术
公开(公告)号：US07418690B1
公开(公告)日：2008-08-26
申请号：US11119070
申请日：2005-04-29
申请人： Babette Van Antwerpen
发明人： Babette Van Antwerpen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.
摘要翻译：本地搜索用于改进可编程逻辑集成电路的技术映射。局部搜索算法被应用于将网表中的逻辑门映射到可编程逻辑IC上的查找表（LUT）的解决方案。本地搜索算法将一系列局部移动应用于解决方案。在每次移动时，提出了对LUT映射的一个小的改变，并且计算了该LUT映射变化的成本变化。如果成本提高，则接受更改并将LUT映射替换为更改的LUT映射。否则，解决方案的更改将被拒绝或以取决于成本变化的概率来接受。可以选择成本函数来表示LUT映射的一个或多个特征，例如面积，速度，功耗或其组合。

8. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

9. 发明公开

US20240184966A1 FPGA Compiler Flow for Heterogeneous Programmable Logic Elements 审中-公开
公开(公告)号：US20240184966A1
公开(公告)日：2024-06-06
申请号：US18401026
申请日：2023-12-29
申请人： Babette Van Antwerpen , Anthea Au , Selvin Quadro , Mahesh Iyer , Grace Zgheib
发明人： Babette Van Antwerpen , Anthea Au , Selvin Quadro , Mahesh Iyer , Grace Zgheib
IPC分类号： G06F30/343
CPC分类号： G06F30/343
摘要： Embodiments herein are directed to systems and techniques for supporting heterogeneous logic architecture in programmable devices, such as field-programmable gate arrays (FPGAs). heterogeneous logic architectures may include additional logic elements (e.g., AND-inverter cones (AICs)) in addition to lookup tables (LUTs). Accordingly, it may be desirable to provide a compiler flow that supports heterogeneous FPGA architecture, taking advantage of a combination of LUTs and other logic elements (e.g., AICs) to improve resource utilization (e.g., die area, wire length) and improve maximum clock frequency and compile time.

10. 发明授权

US08661380B1 Method and apparatus for performing parallel synthesis on a field programmable gate array 有权
标题翻译：用于在现场可编程门阵列上执行并行合成的方法和装置
公开(公告)号：US08661380B1
公开(公告)日：2014-02-25
申请号：US12070478
申请日：2008-02-19
申请人： Gregg William Baeckler , Babette Van Antwerpen
发明人： Gregg William Baeckler , Babette Van Antwerpen
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.
摘要翻译：用于设计要在目标设备上实现的系统的方法包括在具有第一设置的系统的整个设计上执行第一合成运行，以生成用于系统的整个设计的第一单元网络列表。在具有第二设置的系统的整个设计上执行第二合成运行，并且与第一合成过程并行地执行以产生用于系统的整个设计的第二单元网表。生成包括来自第一网表的逻辑的第一部分和来自第二小区网表的逻辑的第二部分的合并的小区网表。

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