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1. 发明授权

US06368910B1 Method of fabricating ruthenium-based contact plug for memory devices 有权
标题翻译：制造用于存储器件的钌基接触插塞的方法
公开(公告)号：US06368910B1
公开(公告)日：2002-04-09
申请号：US09721796
申请日：2000-11-24
申请人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
发明人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/76877 , H01L23/485 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.
摘要翻译：一种用于制造诸如动态随机存取存储器（DRAM）和铁电随机存取存储器（FRAM）的半导体存储器单元的方法，其具有改善的电容器电极和下面的器件区域之间的接触。它包括以下主要步骤：（1）在晶片表面上形成第一电介质层; （2）在所述第一电介质层中形成至少一个通孔; （3）在通孔中形成钌基塞; 和（4）形成与钌基塞接触的电容器。钌基塞可以由钌金属，导电氧化钌或导电氧化钌和金属钌的叠层制成。该方法允许在不需要屏蔽的情况下制造存储单元，这是在制造过程中保护存储电极不与Si原子反应所需要的。

2. 发明授权

US06764863B2 Memory-storage node and the method of fabricating the same 有权
标题翻译：存储器节点及其制造方法
公开(公告)号：US06764863B2
公开(公告)日：2004-07-20
申请号：US10387476
申请日：2003-03-14
申请人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
摘要翻译：本发明的存储器存储节点包括半导体衬底，衬底上的第一绝缘层，形成在第一绝缘层内的导电层，以及形成在导电层上的阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。存储器存储节点还包括位于阻挡层上的第一电极，位于第一电极上的电介质层，以及介电层上的第二电极。本发明的存储器存储器的制造方法提供半导体衬底，并在衬底上形成第一绝缘层。在第一绝缘层中形成第一开口，并且在第一开口中设置导电层。然后在第一开口中和导电层上方形成阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。在第一绝缘层和阻挡层之上形成第二绝缘层。在第二绝缘层中形成第二开口以暴露下面的阻挡层的一部分。第一电极形成在第二开口中，并且在第二绝缘层和第一电极上形成电介质层。最后，在电介质层上形成第二电极。

3. 发明授权

US06563161B2 Memory-storage node and the method of fabricating the same 有权
公开(公告)号：US06563161B2
公开(公告)日：2003-05-13
申请号：US09813993
申请日：2001-03-22
申请人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

4. 发明申请

US20070111420A1 CMOS AND MOS DEVICE 审中-公开
标题翻译： CMOS和MOS器件
公开(公告)号：US20070111420A1
公开(公告)日：2007-05-17
申请号：US11309204
申请日：2006-07-13
申请人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
发明人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first active region and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate; the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括衬底，第一类型的金属氧化物半导体（MOS）晶体管，第二类型的MOS晶体管，蚀刻停止层，第一应力层和第二应力层被提供。衬底具有第一有源区和第二有源区。第一有源区通过隔离结构与第二有源区隔离。第一类型的MOS晶体管设置在基板的第一有源区中; 第二类型的MOS晶体管设置在衬底的第二有源区中。蚀刻停止层适合地覆盖第一类型的MOS晶体管，第二类型的MOS晶体管和隔离结构。第一应力层设置在第一有源区中的蚀刻停止层上，第二应力层设置在第二有源区中的蚀刻停止层上。

5. 发明授权

US08129101B2 Method for increasing the removal rate of photoresist layer 有权
标题翻译：提高光致抗蚀剂层去除率的方法
公开(公告)号：US08129101B2
公开(公告)日：2012-03-06
申请号：US12399019
申请日：2009-03-06
申请人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
发明人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
IPC分类号： G03F7/26
CPC分类号： H01L21/0206 , G03F7/427 , H01L21/31133 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/963
摘要： A method for increasing the removal rate of a photoresist layer is provided. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.
摘要翻译：提供了增加光致抗蚀剂层的去除速率的方法。该方法包括在形成光致抗蚀剂层之前对诸如等离子体工艺的衬底进行预处理。该方法可以应用于半导体器件的制造，以增加光致抗蚀剂层的去除速率。

6. 发明申请

US20080102643A1 PATTERNING METHOD 审中-公开
标题翻译：绘图方法
公开(公告)号：US20080102643A1
公开(公告)日：2008-05-01
申请号：US11554600
申请日：2006-10-31
申请人： Yi-Hsing Chen , Meng-Jun Wang , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Yi-Hsing Chen , Meng-Jun Wang , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/31138 , H01L21/32139 , H01L21/76224 , H01L21/76802
摘要： A patterning method is provided. The method includes the steps of firstly forming an underlying layer, a silicon rich organic layer, and a photoresist layer on the material layer in succession. The photoresist layer is patterned, and the silicon rich organic layer is etched using the photoresist layer as a mask. Then, an etching process is performed to pattern the underlying layer using the silicon rich organic layer as a mask. Reactive gases adopted in the etching process include a passivation gas, an etching gas, and a carrier gas. The passivation gas forms a passivation layer at side walls of the patterned underlying layer during the etching process. After that, the material layer is etched using the underlying layer as a mask to form an opening in material layer. Finally, the underlying layer is removed.
摘要翻译：提供了图案化方法。该方法包括以下步骤：首先在材料层上依次形成下层，富硅有机层和光致抗蚀剂层。对光致抗蚀剂层进行图案化，使用光致抗蚀剂层作为掩模蚀刻富硅有机层。然后，使用富硅有机层作为掩模进行蚀刻工艺以对下层进行图案化。在蚀刻工艺中采用的反应气体包括钝化气体，蚀刻气体和载气。钝化气体在蚀刻工艺期间在图案化的下层的侧壁处形成钝化层。之后，使用下层作为掩模蚀刻材料层，以在材料层中形成开口。最后，底层被删除。

7. 发明申请

US20070111452A1 FABRICATING METHOD OF CMOS AND MOS DEVICE 有权
标题翻译： CMOS和MOS器件的制作方法
公开(公告)号：US20070111452A1
公开(公告)日：2007-05-17
申请号：US11164274
申请日：2005-11-16
申请人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
发明人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括衬底，第一类型的金属氧化物半导体（MOS）晶体管，第二类型的MOS晶体管，蚀刻停止层，第一应力层和第二应力层被提供。衬底具有第一和第二有源区。第一有源区通过隔离结构与第二有源区隔离。第一类型的MOS晶体管设置在衬底的第一有源区中，并且第二类型的MOS晶体管设置在衬底的第二有源区中。蚀刻停止层适合地覆盖第一类型的MOS晶体管，第二类型的MOS晶体管和隔离结构。第一应力层设置在第一有源区中的蚀刻停止层上，第二应力层设置在第二有源区中的蚀刻停止层上。

8. 发明申请

US20070093031A1 METHODS OF REMOVING PHOTORESIST AND FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：去除光电子元件和制造半导体器件的方法
公开(公告)号：US20070093031A1
公开(公告)日：2007-04-26
申请号：US11163469
申请日：2005-10-20
申请人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
发明人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
IPC分类号： H01L21/336
CPC分类号： H01L21/0206 , G03F7/427 , H01L21/31133 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/963
摘要： A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.
摘要翻译：用于增加用作离子注入掩模的光致抗蚀剂层的去除速率的方法。该方法包括在形成光致抗蚀剂层之前对诸如等离子体工艺的衬底进行预处理。该方法可以应用于半导体器件的制造，以增加光致抗蚀剂层的去除速率。

9. 发明授权

US07851370B2 Patterning method 有权
标题翻译：图案化方法
公开(公告)号：US07851370B2
公开(公告)日：2010-12-14
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译：提供了图案化方法。在图案化方法中，在基板上形成膜，并测量预层信息。接下来，进行蚀刻处理以蚀刻该膜。蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设置用于进行延长蚀刻步骤的延长蚀刻时间，以获得所需的膜轮廓。

10. 发明申请

US20090258500A1 METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR 有权
标题翻译：形成半导体器件的图案的方法和形成相关MOS晶体管的方法
公开(公告)号：US20090258500A1
公开(公告)日：2009-10-15
申请号：US12101122
申请日：2008-04-10
申请人： Min-Chieh Yang , Lung-En Kuo
发明人： Min-Chieh Yang , Lung-En Kuo
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
摘要翻译：一种形成半导体器件的图案的方法，其中在上部旋涂玻璃（SOG）层和下部蚀刻目标层之间包括两个硬掩模。 SOG层分别通过两个不同的图案化光致抗蚀剂蚀刻两次以在SOG层中形成精细图案。随后，通过利用图案化的SOG层作为蚀刻掩模来蚀刻上部硬掩模，因此上部图案化的硬掩模可以具有声音形状和足够厚度的精细图案。此后，通过利用上部图案化的硬掩模作为蚀刻掩模来蚀刻下部硬掩模和蚀刻目标层，因此可以很好地保护被两个硬掩模覆盖的蚀刻目标层的部分免受蚀刻处理。

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