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1. 发明申请

US20130257763A1 ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备
公开(公告)号：US20130257763A1
公开(公告)日：2013-10-03
申请号：US13783397
申请日：2013-03-04
申请人： Tung-Tsan Lee , Min-Chieh Yang , Ying-Hao Chiu
发明人： Tung-Tsan Lee , Min-Chieh Yang , Ying-Hao Chiu
IPC分类号： G09G5/00 , G06F3/041
CPC分类号： G09G5/005 , G06F3/0412 , G06F3/147
摘要： An electronic device includes a computing module and a display module. The computing module executes a first operating system. When the display module is in a connection area with the computing module, the display module displays an image of the first operating system. When the display module is outside the connection area, the display module executes a second operating system, and displays an image of the second operating system.
摘要翻译：电子设备包括计算模块和显示模块。计算模块执行第一操作系统。当显示模块处于与计算模块的连接区域中时，显示模块显示第一操作系统的图像。当显示模块在连接区域之外时，显示模块执行第二操作系统，并显示第二操作系统的图像。

2. 发明授权

US07709275B2 Method of forming a pattern for a semiconductor device and method of forming the related MOS transistor 有权
标题翻译：形成半导体器件的图案的方法和形成相关的MOS晶体管的方法
公开(公告)号：US07709275B2
公开(公告)日：2010-05-04
申请号：US12101122
申请日：2008-04-10
申请人： Min-Chieh Yang , Lung-En Kuo
发明人： Min-Chieh Yang , Lung-En Kuo
IPC分类号： H01L21/00
CPC分类号： H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
摘要翻译：一种形成半导体器件的图案的方法，其中在上部旋涂玻璃（SOG）层和下部蚀刻目标层之间包括两个硬掩模。 SOG层分别通过两个不同的图案化光致抗蚀剂蚀刻两次以在SOG层中形成精细图案。随后，通过利用图案化的SOG层作为蚀刻掩模来蚀刻上部硬掩模，因此上部图案化的硬掩模可以具有声音形状和足够厚度的精细图案。此后，通过利用上部图案化的硬掩模作为蚀刻掩模来蚀刻下部硬掩模和蚀刻目标层，因此可以很好地保护被两个硬掩模覆盖的蚀刻目标层的部分免受蚀刻处理。

3. 发明授权

US07592265B2 Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor 有权
标题翻译：修整硬掩模层的方法，在MOS晶体管中制造栅极的方法和用于制造MOS晶体管中的栅极的堆叠
公开(公告)号：US07592265B2
公开(公告)日：2009-09-22
申请号：US11620028
申请日：2007-01-04
申请人： Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
发明人： Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32139 , H01L21/7624 , H01L29/6659 , H01L29/7833 , Y10S438/947 , Y10S438/95
摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.
摘要翻译：提供了修剪硬掩模的方法。该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。在硬掩模层上进行修整处理。本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。

4. 发明申请

US20090206403A1 METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR 审中-公开
标题翻译：用于制造硬掩模层的方法，用于在MOS晶体管中形成栅极的方法，以及用于在MOS晶体管中形成栅极的堆叠
公开(公告)号：US20090206403A1
公开(公告)日：2009-08-20
申请号：US12430107
申请日：2009-04-27
申请人： Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
发明人： Meng-Jun Wang , Yi-Hsing Chen , Min-Chieh Yang , Jiunn-Hsiung Liao
IPC分类号： H01L29/06
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32139 , H01L21/7624 , H01L29/6659 , H01L29/7833 , Y10S438/947 , Y10S438/95
摘要： A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.
摘要翻译：用于形成MOS晶体管的栅极的堆叠结构包括其中包括多个浅沟槽隔离的衬底; 依次形成在基板上的电介质层，导电层和硬掩模层; 以及包括在所述硬掩模层上的顶部光致抗蚀剂层，含硅光刻胶层和底部抗反射涂层（BARC）的三层堆叠，其中所述含硅光致抗蚀剂层包括10-30％的硅并且硬掩模层与导电层具有高蚀刻选择性比。

5. 发明授权

US06563161B2 Memory-storage node and the method of fabricating the same 有权
公开(公告)号：US06563161B2
公开(公告)日：2003-05-13
申请号：US09813993
申请日：2001-03-22
申请人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

6. 发明申请

US20070111420A1 CMOS AND MOS DEVICE 审中-公开
标题翻译： CMOS和MOS器件
公开(公告)号：US20070111420A1
公开(公告)日：2007-05-17
申请号：US11309204
申请日：2006-07-13
申请人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
发明人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first active region and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate; the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括衬底，第一类型的金属氧化物半导体（MOS）晶体管，第二类型的MOS晶体管，蚀刻停止层，第一应力层和第二应力层被提供。衬底具有第一有源区和第二有源区。第一有源区通过隔离结构与第二有源区隔离。第一类型的MOS晶体管设置在基板的第一有源区中; 第二类型的MOS晶体管设置在衬底的第二有源区中。蚀刻停止层适合地覆盖第一类型的MOS晶体管，第二类型的MOS晶体管和隔离结构。第一应力层设置在第一有源区中的蚀刻停止层上，第二应力层设置在第二有源区中的蚀刻停止层上。

7. 发明授权

US07851370B2 Patterning method 有权
标题翻译：图案化方法
公开(公告)号：US07851370B2
公开(公告)日：2010-12-14
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译：提供了图案化方法。在图案化方法中，在基板上形成膜，并测量预层信息。接下来，进行蚀刻处理以蚀刻该膜。蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设置用于进行延长蚀刻步骤的延长蚀刻时间，以获得所需的膜轮廓。

8. 发明申请

US20090258500A1 METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR 有权
标题翻译：形成半导体器件的图案的方法和形成相关MOS晶体管的方法
公开(公告)号：US20090258500A1
公开(公告)日：2009-10-15
申请号：US12101122
申请日：2008-04-10
申请人： Min-Chieh Yang , Lung-En Kuo
发明人： Min-Chieh Yang , Lung-En Kuo
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
摘要翻译：一种形成半导体器件的图案的方法，其中在上部旋涂玻璃（SOG）层和下部蚀刻目标层之间包括两个硬掩模。 SOG层分别通过两个不同的图案化光致抗蚀剂蚀刻两次以在SOG层中形成精细图案。随后，通过利用图案化的SOG层作为蚀刻掩模来蚀刻上部硬掩模，因此上部图案化的硬掩模可以具有声音形状和足够厚度的精细图案。此后，通过利用上部图案化的硬掩模作为蚀刻掩模来蚀刻下部硬掩模和蚀刻目标层，因此可以很好地保护被两个硬掩模覆盖的蚀刻目标层的部分免受蚀刻处理。

9. 发明申请

US20090169767A1 METHOD FOR INCREASING THE REMOVAL RATE OF PHOTORESIST LAYER 有权
标题翻译：增加光电层移除速率的方法
公开(公告)号：US20090169767A1
公开(公告)日：2009-07-02
申请号：US12399019
申请日：2009-03-06
申请人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
发明人： Wen-Hsien Huang , Min-Chieh Yang , Jiunn-Hsing Liao
IPC分类号： H05H1/24 , B05D3/00
CPC分类号： H01L21/0206 , G03F7/427 , H01L21/31133 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/963
摘要： A method for increasing the removal rate of a photoresist layer is provided. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.
摘要翻译：提供了增加光致抗蚀剂层的去除速率的方法。该方法包括在形成光致抗蚀剂层之前对诸如等离子体工艺的衬底进行预处理。该方法可以应用于半导体器件的制造，以增加光致抗蚀剂层的去除速率。

10. 发明申请

US20080096343A1 FABRICATING METHOD OF CMOS 有权
标题翻译： CMOS制作方法
公开(公告)号：US20080096343A1
公开(公告)日：2008-04-24
申请号：US11924571
申请日：2007-10-25
申请人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
发明人： Pei-Yu Chou , Min-Chieh Yang , Wen-Han Hung
IPC分类号： H01L21/98
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.
摘要翻译：提供一种形成金属氧化物半导体（MOS）器件的方法。该方法包括以下步骤。首先，在基板上形成导电型MOS晶体管。然后，在基板上形成第一蚀刻停止层，以覆盖适形的导电型MOS晶体管。此后，在第一蚀刻停止层上形成应力层。然后，在应力层上形成第二蚀刻停止层。

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